div3.map.qmsg

VHDL实现50％占空比。并且是奇数分频。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 20 21:53:46 2006 " "Info: Processing started: Wed Sep 20 21:53:46 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off div3 -c div3 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off div3 -c div3" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div3.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div3.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div3-behavioral " "Info: Found design unit 1: div3-behavioral" {  } { { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 div3 " "Info: Found entity 1: div3" {  } { { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "div3 " "Info: Elaborating entity \"div3\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count1 div3.vhd(15) " "Warning: VHDL Process Statement warning at div3.vhd(15): signal \"count1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count2 div3.vhd(23) " "Warning: VHDL Process Statement warning at div3.vhd(23): signal \"count2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count3 div3.vhd(32) " "Warning: VHDL Process Statement warning at div3.vhd(32): signal \"count3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count4 div3.vhd(40) " "Warning: VHDL Process Statement warning at div3.vhd(40): signal \"count4\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 40 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "23 " "Info: Implemented 23 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "18 " "Info: Implemented 18 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 20 21:53:48 2006 " "Info: Processing ended: Wed Sep 20 21:53:48 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}