div3.tan.qmsg

VHDL实现50％占空比。并且是奇数分频。

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register count4\[0\] count4\[1\] 405.19 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 405.19 MHz between source register \"count4\[0\]\" and destination register \"count4\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.234 ns 1.234 ns 2.468 ns " "Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.114 ns + Longest register register " "Info: + Longest register to register delay is 1.114 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count4\[0\] 1 REG LC_X26_Y6_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y6_N2; Fanout = 3; REG Node = 'count4\[0\]'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "" { count4[0] } "NODE_NAME" } "" } } { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.447 ns) + CELL(0.667 ns) 1.114 ns count4\[1\] 2 REG LC_X26_Y6_N5 1 " "Info: 2: + IC(0.447 ns) + CELL(0.667 ns) = 1.114 ns; Loc. = LC_X26_Y6_N5; Fanout = 1; REG Node = 'count4\[1\]'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "1.114 ns" { count4[0] count4[1] } "NODE_NAME" } "" } } { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.667 ns 59.87 % " "Info: Total cell delay = 0.667 ns ( 59.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.447 ns 40.13 % " "Info: Total interconnect delay = 0.447 ns ( 40.13 % )" {  } {  } 0}  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "1.114 ns" { count4[0] count4[1] } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus50/bin/Technology_Viewer.qrui" "1.114 ns" { count4[0] count4[1] } { 0.000ns 0.447ns } { 0.000ns 0.667ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.155 ns - Smallest " "Info: - Smallest clock skew is -0.155 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.967 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.967 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "" { clk } "NODE_NAME" } "" } } { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.429 ns) + CELL(0.720 ns) 2.279 ns f3 2 REG LC_X8_Y6_N0 2 " "Info: 2: + IC(0.429 ns) + CELL(0.720 ns) = 2.279 ns; Loc. = LC_X8_Y6_N0; Fanout = 2; REG Node = 'f3'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "1.149 ns" { clk f3 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.395 ns) + CELL(0.088 ns) 2.762 ns f5~0 3 COMB LC_X8_Y6_N2 7 " "Info: 3: + IC(0.395 ns) + CELL(0.088 ns) = 2.762 ns; Loc. = LC_X8_Y6_N2; Fanout = 7; COMB Node = 'f5~0'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "0.483 ns" { f3 f5~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.658 ns) + CELL(0.547 ns) 5.967 ns count4\[1\] 4 REG LC_X26_Y6_N5 1 " "Info: 4: + IC(2.658 ns) + CELL(0.547 ns) = 5.967 ns; Loc. = LC_X26_Y6_N5; Fanout = 1; REG Node = 'count4\[1\]'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "3.205 ns" { f5~0 count4[1] } "NODE_NAME" } "" } } { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.485 ns 41.65 % " "Info: Total cell delay = 2.485 ns ( 41.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.482 ns 58.35 % " "Info: Total interconnect delay = 3.482 ns ( 58.35 % )" {  } {  } 0}  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "5.967 ns" { clk f3 f5~0 count4[1] } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus50/bin/Technology_Viewer.qrui" "5.967 ns" { clk clk~out0 f3 f5~0 count4[1] } { 0.000ns 0.000ns 0.429ns 0.395ns 2.658ns } { 0.000ns 1.130ns 0.720ns 0.088ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.122 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.122 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "" { clk } "NODE_NAME" } "" } } { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.429 ns) + CELL(0.720 ns) 2.279 ns f4 2 REG LC_X8_Y6_N9 2 " "Info: 2: + IC(0.429 ns) + CELL(0.720 ns) = 2.279 ns; Loc. = LC_X8_Y6_N9; Fanout = 2; REG Node = 'f4'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "1.149 ns" { clk f4 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.413 ns) + CELL(0.225 ns) 2.917 ns f5~0 3 COMB LC_X8_Y6_N2 7 " "Info: 3: + IC(0.413 ns) + CELL(0.225 ns) = 2.917 ns; Loc. = LC_X8_Y6_N2; Fanout = 7; COMB Node = 'f5~0'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "0.638 ns" { f4 f5~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.658 ns) + CELL(0.547 ns) 6.122 ns count4\[0\] 4 REG LC_X26_Y6_N2 3 " "Info: 4: + IC(2.658 ns) + CELL(0.547 ns) = 6.122 ns; Loc. = LC_X26_Y6_N2; Fanout = 3; REG Node = 'count4\[0\]'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "3.205 ns" { f5~0 count4[0] } "NODE_NAME" } "" } } { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.622 ns 42.83 % " "Info: Total cell delay = 2.622 ns ( 42.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns 57.17 % " "Info: Total interconnect delay = 3.500 ns ( 57.17 % )" {  } {  } 0}  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "6.122 ns" { clk f4 f5~0 count4[0] } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus50/bin/Technology_Viewer.qrui" "6.122 ns" { clk clk~out0 f4 f5~0 count4[0] } { 0.000ns 0.000ns 0.429ns 0.413ns 2.658ns } { 0.000ns 1.130ns 0.720ns 0.225ns 0.547ns } } }  } 0}  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "5.967 ns" { clk f3 f5~0 count4[1] } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus50/bin/Technology_Viewer.qrui" "5.967 ns" { clk clk~out0 f3 f5~0 count4[1] } { 0.000ns 0.000ns 0.429ns 0.395ns 2.658ns } { 0.000ns 1.130ns 0.720ns 0.088ns 0.547ns } } } { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "6.122 ns" { clk f4 f5~0 count4[0] } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus50/bin/Technology_Viewer.qrui" "6.122 ns" { clk clk~out0 f4 f5~0 count4[0] } { 0.000ns 0.000ns 0.429ns 0.413ns 2.658ns } { 0.000ns 1.130ns 0.720ns 0.225ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 10 -1 0 } }  } 0}  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "1.114 ns" { count4[0] count4[1] } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus50/bin/Technology_Viewer.qrui" "1.114 ns" { count4[0] count4[1] } { 0.000ns 0.447ns } { 0.000ns 0.667ns } } } { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "5.967 ns" { clk f3 f5~0 count4[1] } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus50/bin/Technology_Viewer.qrui" "5.967 ns" { clk clk~out0 f3 f5~0 count4[1] } { 0.000ns 0.000ns 0.429ns 0.395ns 2.658ns } { 0.000ns 1.130ns 0.720ns 0.088ns 0.547ns } } } { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "6.122 ns" { clk f4 f5~0 count4[0] } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus50/bin/Technology_Viewer.qrui" "6.122 ns" { clk clk~out0 f4 f5~0 count4[0] } { 0.000ns 0.000ns 0.429ns 0.413ns 2.658ns } { 0.000ns 1.130ns 0.720ns 0.225ns 0.547ns } } }  } 0}  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "" { count4[1] } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus50/bin/Technology_Viewer.qrui" "" { count4[1] } {  } {  } } } { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 10 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk f6 f8 9.473 ns register " "Info: tco from clock \"clk\" to destination pin \"f6\" through register \"f8\" is 9.473 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.092 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.092 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "" { clk } "NODE_NAME" } "" } } { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.429 ns) + CELL(0.720 ns) 2.279 ns f4 2 REG LC_X8_Y6_N9 2 " "Info: 2: + IC(0.429 ns) + CELL(0.720 ns) = 2.279 ns; Loc. = LC_X8_Y6_N9; Fanout = 2; REG Node = 'f4'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "1.149 ns" { clk f4 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.413 ns) + CELL(0.225 ns) 2.917 ns f5~0 3 COMB LC_X8_Y6_N2 7 " "Info: 3: + IC(0.413 ns) + CELL(0.225 ns) = 2.917 ns; Loc. = LC_X8_Y6_N2; Fanout = 7; COMB Node = 'f5~0'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "0.638 ns" { f4 f5~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.628 ns) + CELL(0.547 ns) 6.092 ns f8 4 REG LC_X22_Y1_N2 1 " "Info: 4: + IC(2.628 ns) + CELL(0.547 ns) = 6.092 ns; Loc. = LC_X22_Y1_N2; Fanout = 1; REG Node = 'f8'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "3.175 ns" { f5~0 f8 } "NODE_NAME" } "" } } { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.622 ns 43.04 % " "Info: Total cell delay = 2.622 ns ( 43.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.470 ns 56.96 % " "Info: Total interconnect delay = 3.470 ns ( 56.96 % )" {  } {  } 0}  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "6.092 ns" { clk f4 f5~0 f8 } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus50/bin/Technology_Viewer.qrui" "6.092 ns" { clk clk~out0 f4 f5~0 f8 } { 0.000ns 0.000ns 0.429ns 0.413ns 2.628ns } { 0.000ns 1.130ns 0.720ns 0.225ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.208 ns + Longest register pin " "Info: + Longest register to pin delay is 3.208 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns f8 1 REG LC_X22_Y1_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y1_N2; Fanout = 1; REG Node = 'f8'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "" { f8 } "NODE_NAME" } "" } } { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.412 ns) + CELL(0.225 ns) 0.637 ns f6~0 2 COMB LC_X22_Y1_N4 1 " "Info: 2: + IC(0.412 ns) + CELL(0.225 ns) = 0.637 ns; Loc. = LC_X22_Y1_N4; Fanout = 1; COMB Node = 'f6~0'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "0.637 ns" { f8 f6~0 } "NODE_NAME" } "" } } { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.949 ns) + CELL(1.622 ns) 3.208 ns f6 3 PIN PIN_48 0 " "Info: 3: + IC(0.949 ns) + CELL(1.622 ns) = 3.208 ns; Loc. = PIN_48; Fanout = 0; PIN Node = 'f6'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "2.571 ns" { f6~0 f6 } "NODE_NAME" } "" } } { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.847 ns 57.57 % " "Info: Total cell delay = 1.847 ns ( 57.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.361 ns 42.43 % " "Info: Total interconnect delay = 1.361 ns ( 42.43 % )" {  } {  } 0}  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "3.208 ns" { f8 f6~0 f6 } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus50/bin/Technology_Viewer.qrui" "3.208 ns" { f8 f6~0 f6 } { 0.000ns 0.412ns 0.949ns } { 0.000ns 0.225ns 1.622ns } } }  } 0}  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "6.092 ns" { clk f4 f5~0 f8 } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus50/bin/Technology_Viewer.qrui" "6.092 ns" { clk clk~out0 f4 f5~0 f8 } { 0.000ns 0.000ns 0.429ns 0.413ns 2.628ns } { 0.000ns 1.130ns 0.720ns 0.225ns 0.547ns } } } { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "3.208 ns" { f8 f6~0 f6 } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus50/bin/Technology_Viewer.qrui" "3.208 ns" { f8 f6~0 f6 } { 0.000ns 0.412ns 0.949ns } { 0.000ns 0.225ns 1.622ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 20 21:54:00 2006 " "Info: Processing ended: Wed Sep 20 21:54:00 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}