div3.fit.eqn

VHDL实现50％占空比。并且是奇数分频。

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--f3 is f3 at LC_X8_Y6_N0
--operation mode is normal

f3_lut_out = VCC;
f3 = DFFEAS(f3_lut_out, GLOBAL(clk), !GLOBAL(A1L42), , , , , , );


--f4 is f4 at LC_X8_Y6_N9
--operation mode is normal

f4_lut_out = VCC;
f4 = DFFEAS(f4_lut_out, !GLOBAL(clk), !GLOBAL(A1L52), , , , , , );


--A1L91 is f5~0 at LC_X8_Y6_N2
--operation mode is normal

A1L91 = !f3 # !f4;


--f7 is f7 at LC_X22_Y1_N5
--operation mode is normal

f7_lut_out = VCC;
f7 = DFFEAS(f7_lut_out, !GLOBAL(A1L91), !GLOBAL(A1L62), , , , , , );


--f8 is f8 at LC_X22_Y1_N2
--operation mode is normal

f8_lut_out = VCC;
f8 = DFFEAS(f8_lut_out, GLOBAL(A1L91), !GLOBAL(A1L72), , , , , , );


--A1L12 is f6~0 at LC_X22_Y1_N4
--operation mode is normal

A1L12 = f8 & f7;


--count1[0] is count1[0] at LC_X7_Y5_N2
--operation mode is normal

count1[0]_lut_out = !count1[0];
count1[0] = DFFEAS(count1[0]_lut_out, GLOBAL(clk), !GLOBAL(A1L42), , , , , , );


--count1[1] is count1[1] at LC_X7_Y5_N4
--operation mode is normal

count1[1]_lut_out = VCC;
count1[1] = DFFEAS(count1[1]_lut_out, GLOBAL(clk), !GLOBAL(A1L42), , count1[0], , , , );


--A1L42 is reduce_nor~0 at LC_X7_Y5_N5
--operation mode is normal

A1L42 = count1[1] & count1[0];


--count2[1] is count2[1] at LC_X9_Y6_N4
--operation mode is normal

count2[1]_lut_out = VCC;
count2[1] = DFFEAS(count2[1]_lut_out, !GLOBAL(clk), !GLOBAL(A1L52), , count2[0], , , , );


--count2[0] is count2[0] at LC_X9_Y6_N2
--operation mode is normal

count2[0]_lut_out = !count2[0];
count2[0] = DFFEAS(count2[0]_lut_out, !GLOBAL(clk), !GLOBAL(A1L52), , , , , , );


--A1L52 is reduce_nor~1 at LC_X8_Y6_N5
--operation mode is normal

A1L52 = count2[0] & count2[1];


--count3[1] is count3[1] at LC_X24_Y6_N4
--operation mode is normal

count3[1]_lut_out = VCC;
count3[1] = DFFEAS(count3[1]_lut_out, !GLOBAL(A1L91), !GLOBAL(A1L62), , count3[0], , , , );


--count3[0] is count3[0] at LC_X24_Y6_N2
--operation mode is normal

count3[0]_lut_out = !count3[0];
count3[0] = DFFEAS(count3[0]_lut_out, !GLOBAL(A1L91), !GLOBAL(A1L62), , , , , , );


--A1L62 is reduce_nor~2 at LC_X26_Y6_N4
--operation mode is normal

A1L62 = count3[0] & count3[1];


--count4[1] is count4[1] at LC_X26_Y6_N5
--operation mode is normal

count4[1]_lut_out = VCC;
count4[1] = DFFEAS(count4[1]_lut_out, GLOBAL(A1L91), !GLOBAL(A1L72), , count4[0], , , , );


--count4[0] is count4[0] at LC_X26_Y6_N2
--operation mode is normal

count4[0]_lut_out = !count4[0];
count4[0] = DFFEAS(count4[0]_lut_out, GLOBAL(A1L91), !GLOBAL(A1L72), , , , , , );


--A1L72 is reduce_nor~3 at LC_X26_Y6_N6
--operation mode is normal

A1L72 = count4[0] & count4[1];


--clk is clk at PIN_10
--operation mode is input

clk = INPUT();


--f is f at PIN_35
--operation mode is output

f = OUTPUT(!A1L91);


--f1 is f1 at PIN_34
--operation mode is output

f1 = OUTPUT(f3);


--f2 is f2 at PIN_29
--operation mode is output

f2 = OUTPUT(f4);


--f6 is f6 at PIN_48
--operation mode is output

f6 = OUTPUT(A1L12);