dct.vhd

用verilog语言实现DCT编解码 附有DCT的说明

   END PROCESS;


-- write function
P_ram1: process (RST,CLK)
begin
if (RST = '1') then
ram1_mem(0 to 63) <= (others => "00000000000");
 elsif (rising_edge (CLK)) then
	if (en_ram1reg = '1' and wr_cntr(6) <= '0' ) then
	  ram1_mem(CONV_INTEGER (wr_cntr(5 downto 0))) <= z_out;
    end if;
 end if;
end process P_ram1;

P_ram2: process (RST,CLK)
begin
if (RST = '1') then
ram2_mem(0 to 63) <= (others => "00000000000");
 elsif (rising_edge (CLK)) then
	if (en_ram1reg = '1' and wr_cntr(6) > '1') then
	  ram2_mem(CONV_INTEGER (wr_cntr(5 downto 0))) <= z_out;
    end if;
 end if;
end process P_ram2;


   PROCESS (CLK)
   BEGIN
      IF (CLK'EVENT AND CLK = '1') THEN
         IF (en_ram1reg = '1' AND rd_cntr(6) = '0') THEN
            data_out <= ram2_mem(CONV_INTEGER (rd_cntr(5 downto 0)));    
         ELSE
            IF (en_ram1reg = '1' AND rd_cntr(6) = '1') THEN
               data_out <= ram1_mem(CONV_INTEGER (rd_cntr(5 downto 0)));    
            ELSE
               data_out <= "00000000000";    
            END IF;
         END IF;
      END IF;
   END PROCESS;

   -- END MEMORY SECTION 
   -- 2D-DCT implementation same as the 1D-DCT implementation 
   -- First dct coeeficient appears at the output of the RAM1 after
   --  First dct coeeficient appears at the output of the RAM1 after
   -- 15 + 64 clk cycles. So the 2nd DCT operation starts after 79 clk cycles. 
   
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         cntr79 <= "0000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         cntr79 <= cntr79 + "0000001";    
      END IF;
   END PROCESS;
   en_dct2d <= '0' WHEN RST = '1' ELSE '1' WHEN (cntr79 = "1001111") ELSE en_dct2d;

   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         en_dct2d_reg <= '0';    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         en_dct2d_reg <= en_dct2d;    
      END IF;
   END PROCESS;
   data_out_final(10 downto 0) <= data_out ;

   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         xb0_in <= "00000000000";    xb1_in <= "00000000000";    
         xb2_in <= "00000000000";    xb3_in <= "00000000000";    
         xb4_in <= "00000000000";    xb5_in <= "00000000000";    
         xb6_in <= "00000000000";    xb7_in <= "00000000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (en_dct2d_reg = '1') THEN
            xb0_in <= data_out_final;    xb1_in <= xb0_in;    
            xb2_in <= xb1_in;    xb3_in <= xb2_in;    
            xb4_in <= xb3_in;    xb5_in <= xb4_in;    
            xb6_in <= xb5_in;    xb7_in <= xb6_in;    
         ELSE
            IF (en_dct2d_reg = '0') THEN
               xb0_in <= "00000000000";    xb1_in <= "00000000000";    
               xb2_in <= "00000000000";    xb3_in <= "00000000000";    
               xb4_in <= "00000000000";    xb5_in <= "00000000000";    
               xb6_in <= "00000000000";    xb7_in <= "00000000000";    
            END IF;
         END IF;
      END IF;
   END PROCESS;

   -- register inputs, inputs read in every eighth clk
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         xb0_reg <= "000000000000";    xb1_reg <= "000000000000";    
         xb2_reg <= "000000000000";    xb3_reg <= "000000000000";    
         xb4_reg <= "000000000000";    xb5_reg <= "000000000000";    
         xb6_reg <= "000000000000";    xb7_reg <= "000000000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (cntr8 = "1000") THEN
            xb0_reg <= xb0_in(10) & xb0_in;    
            xb1_reg <= xb1_in(10) & xb1_in;    
            xb2_reg <= xb2_in(10) & xb2_in;    
            xb3_reg <= xb3_in(10) & xb3_in;    
            xb4_reg <= xb4_in(10) & xb4_in;    
            xb5_reg <= xb5_in(10) & xb5_in;    
            xb6_reg <= xb6_in(10) & xb6_in;    
            xb7_reg <= xb7_in(10) & xb7_in;    
         END IF;
      END IF;
   END PROCESS;

   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         toggleB <= '0';    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         toggleB <= NOT toggleB;    
      END IF;
   END PROCESS;

   -- adder / subtractor block 
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         add_sub1b <= "000000000000";    
         add_sub2b <= "000000000000";    
         add_sub3b <= "000000000000";    
         add_sub4b <= "000000000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (toggleB = '1') THEN
            add_sub1b <= xb0_reg + xb7_reg;    
            add_sub2b <= xb1_reg + xb6_reg;    
            add_sub3b <= xb2_reg + xb5_reg;    
            add_sub4b <= xb3_reg + xb4_reg;    
         ELSE
            IF (toggleB = '0') THEN
               add_sub1b <= xb7_reg - xb0_reg;    
               add_sub2b <= xb6_reg - xb1_reg;    
               add_sub3b <= xb5_reg - xb2_reg;    
               add_sub4b <= xb4_reg - xb3_reg;    
            END IF;
         END IF;
      END IF;
   END PROCESS;

P_comp1b: process (RST,CLK)
begin
  if (RST = '1') then
       addsub1b_comp <= (others => '0'); save_sign1b <= '0';
   elsif (rising_edge (CLK)) then
      if(add_sub1b(11) = '0') then
        addsub1b_comp <= add_sub1b(10 downto 0); save_sign1b <= '0';
      else
        addsub1b_comp <= (not(add_sub1b(10 downto 0))) + '1'; save_sign1b <= '1';
      end if;
   end if;
end process P_comp1b;

P_comp2b: process (RST,CLK)
begin
  if (RST = '1') then
       addsub2b_comp <= (others => '0'); save_sign2b <= '0';
   elsif (rising_edge (CLK)) then
      if(add_sub2b(11) = '0') then
        addsub2b_comp <= add_sub2b(10 downto 0); save_sign2b <= '0';
      else
        addsub2b_comp <= (not(add_sub2b(10 downto 0))) + '1'; save_sign2b <= '1';
      end if;
   end if;
end process P_comp2b;


P_comp3b: process (RST,CLK)
begin
  if (RST = '1') then
       addsub3b_comp <= (others => '0'); save_sign3b <= '0';
   elsif (rising_edge (CLK)) then
      if(add_sub3b(11) = '0') then
        addsub3b_comp <= add_sub3b(10 downto 0); save_sign3b <= '0';
      else
        addsub3b_comp <= (not(add_sub3b(10 downto 0))) + '1'; save_sign3b <= '1';
      end if;
   end if;
end process P_comp3b;

P_comp4b: process (RST,CLK)
begin
  if (RST = '1') then
       addsub4b_comp <= (others => '0'); save_sign4b <= '0';
   elsif (rising_edge (CLK)) then
      if(add_sub4b(11) = '0') then
        addsub4b_comp <= add_sub4b(10 downto 0); save_sign4b <= '0';
      else
        addsub4b_comp <= (not(add_sub4b(10 downto 0))) + '1'; save_sign4b <= '1';
      end if;
   end if;
end process P_comp4b;


   p1b_all <= (addsub1b_comp * memory1a(6 downto 0)) ;
   p2b_all <= (addsub2b_comp * memory2a(6 downto 0)) ;
   p3b_all <= (addsub3b_comp * memory3a(6 downto 0)) ;
   p4b_all <= (addsub4b_comp * memory4a(6 downto 0)) ;


   -- The following instantiation can be used while targetting Virtex2 
   --MULT18X18 mult1b (.A({9'b0,addsub1b_comp}), .B({11'b0,memory1a[6:0]}), .P(p1b_all));
   
   --MULT18X18 mult2b (.A({9'b0,addsub2b_comp}), .B({11'b0,memory2a[6:0]}), .P(p2b_all));
   
   --MULT18X18 mult3b (.A({9'b0,addsub3b_comp}), .B({11'b0,memory3a[6:0]}), .P(p3b_all));
   
   --MULT18X18 mult4b (.A({9'b0,addsub4b_comp}), .B({11'b0,memory4a[6:0]}), .P(p4b_all));
   


xor1b <= (save_sign1b) xor (memory1a(7));
xor2b <= (save_sign2b) xor (memory2a(7));
xor3b <= (save_sign3b) xor (memory3a(7));
xor4b <= (save_sign4b) xor (memory4a(7));

P_prodB: process(CLK,RST)
begin
    if (RST = '1') then
     p1b <= (others =>'0'); p2b <= (others =>'0'); 
     p3b <= (others =>'0'); p4b <= (others =>'0'); 
    elsif (rising_edge (CLK)) then
       if(i_wait = "00") then
          if (xor1b = '1') then p1b <= not("00" & p1b_all(17 downto 0)) + '1'; 
          elsif (xor1b = '0') then p1b <= ("00" & p1b_all(17 downto 0)); end if;
          if (xor2b = '1') then p2b <= not("00" & p2b_all(17 downto 0)) + '1'; 
          elsif (xor2b = '0') then p2b <= ("00" & p2b_all(17 downto 0)); end if;
          if (xor3b = '1') then p3b <= not("00" & p3b_all(17 downto 0)) + '1'; 
          elsif (xor3b = '0') then p3b <= ("00" & p3b_all(17 downto 0)); end if;
          if (xor4b = '1') then p4b <= not("00" & p4b_all(17 downto 0)) + '1'; 
          elsif (xor4b = '0') then p4b <= ("00" & p4b_all(17 downto 0)); end if;
       end if;
    end if;
end process P_prodB;

   --always @ (posedge RST or posedge CLK)
   -- always @ (posedge RST or posedge CLK)
   --   begin
   --     if (RST)
   --       begin
   --         p1b <= 16'b0; p2b <= 16'b0; p3b <= 16'b0; p4b <= 16'b0; //indexj<= 7;
   --       end
   --     else if (i_wait == 2'b00)
   --       begin
   --         p1b <= (save_sign1b ^ memory1a[7]) ? (-addsub1b_comp * memory1a[6:0]) :(addsub1b_comp * memory1a[6:0]);
   --         p2b <= (save_sign2b ^ memory2a[7]) ? (-addsub2b_comp * memory2a[6:0]) :(addsub2b_comp * memory2a[6:0]);
   --         p3b <= (save_sign3b ^ memory3a[7]) ? (-addsub3b_comp * memory3a[6:0]) :(addsub3b_comp * memory3a[6:0]);
   --         p4b <= (save_sign4b ^ memory4a[7]) ? (-addsub4b_comp * memory4a[6:0]) :(addsub4b_comp * memory4a[6:0]);
   --       end
   --   end
   -- 
   
   -- The above if else statement used to get the add_sub signals can also be implemented using  the adsu16 library element as follows 
   --ADSU16 adsu16_5 (.A({8'b0,xb0_reg}), .B({8'b0,xb7_reg}), .ADD(toggleB), .CI(1'b0), .S(add_sub1b), .OFL(open), .CO(open));
   
   --ADSU16 adsu16_6 (.A({8'b0,xb1_reg}), .B({8'b0,xb6_reg}), .ADD(toggleB), .CI(1'b0), .S(add_sub2b), .OFL(open), .CO(open));
   
   --ADSU16 adsu16_7 (.A({8'b0,xb2_reg}), .B({8'b0,xb5_reg}), .ADD(toggleB), .CI(1'b0), .S(add_sub3b), .OFL(open), .CO(open));
   
   --ADSU16 adsu16_8 (.A({8'b0,xb3_reg}), .B({8'b0,xb4_reg}), .ADD(toggleB), .CI(1'b0), .S(add_sub4b), .OFL(open), .CO(open));
   
   -- multiply the outputs of the add/sub block with the 8 sets of stored coefficients 
   -- Final adder. Adding the ouputs of the 4 multipliers 
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         dct2d_int1 <= "00000000000000000000";    
         dct2d_int2 <= "00000000000000000000";    
         dct_2d_int <= "00000000000000000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         dct2d_int1 <= p1b + p2b;    
         dct2d_int2 <= p3b + p4b;    
         dct_2d_int <= dct2d_int1 + dct2d_int2;    
      END IF;
   END PROCESS;
   dct_2d_rnd <= dct_2d_int(19 downto 8) ;
   dct_2d <= (dct_2d_rnd + "000000000001") WHEN dct_2d_int(7) = '1' ELSE dct_2d_rnd;

   -- The first 1D-DCT output becomes valid after 14 +64 clk cycles. For the first 
   --  The first 1D-DCT output becomes valid after 14 +64 clk cycles. For the first 
   -- 2D-DCT output to be valid it takes 78 + 1clk to write into the ram + 1clk to 
   -- write out of the ram + 8 clks to shift in the 1D-DCT values + 1clk to register 
   -- the 1D-DCT values + 1clk to add/sub + 1clk to take compliment + 1 clk for 
   -- multiplying +  2clks to add product. So the 2D-DCT output will be valid 
   -- at the 94th clk. rdy_out goes high at 93rd clk so that the first data is valid
   -- for the next block
   
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         cntr92 <= "0000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (cntr92 < "1011110") THEN
            cntr92 <= cntr92 + "0000001";    
         ELSE
            cntr92 <= cntr92;    
         END IF;
      END IF;
   END PROCESS;
   rdy_out <= '1' WHEN (cntr92 = "1011110") ELSE '0';

END logic;