dct.v

用verilog语言实现DCT编解码 附有DCT的说明

 
end

always @ (posedge CLK)
if (en_ram1reg == 1'b1 && wr_cntr[6] == 1'b0)
ram1_mem[wr_cntr[5:0]] <= z_out;


always @ (posedge CLK)
if (en_ram1reg == 1'b1 && wr_cntr[6] == 1'b1)
ram2_mem[wr_cntr[5:0]] <= z_out;


always @ (posedge CLK)
begin
if (en_ram1reg == 1'b1 && rd_cntr[6] == 1'b0)
  data_out <= ram2_mem[rd_cntr[5:0]];

else if (en_ram1reg == 1'b1 && rd_cntr[6] == 1'b1)
  data_out <= ram1_mem[rd_cntr[5:0]];
else data_out <= 11'b0;
end


/* END MEMORY SECTION */

/* 2D-DCT implementation same as the 1D-DCT implementation */

/* First dct coeeficient appears at the output of the RAM1 after
15 + 64 clk cycles. So the 2nd DCT operation starts after 79 clk cycles. */

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       cntr79 <= 7'b0;
       end
   else
       begin
       cntr79 <= cntr79 + 1;
      end
   end

assign en_dct2d = RST ? 1'b0 : (cntr79 == 7'b1001111) ? 1'b1 : en_dct2d;

always @ (posedge CLK or posedge RST)
        begin
          if (RST)
              begin  en_dct2d_reg <= 1'b0; end
          else
              begin  en_dct2d_reg <= en_dct2d ; end
        end

assign data_out_final[10:0] = data_out;

always @ (posedge CLK or posedge RST )
   begin
   if (RST)
       begin
       xb0_in <= 11'b0; xb1_in <= 11'b0; xb2_in <= 11'b0; xb3_in <= 11'b0;
       xb4_in <= 11'b0; xb5_in <= 11'b0; xb6_in <= 11'b0; xb7_in <= 11'b0;
       end
   else if (en_dct2d_reg == 1'b1) 
       begin
       xb0_in <= data_out_final; xb1_in <= xb0_in; xb2_in <= xb1_in; xb3_in <= xb2_in;
       xb4_in <= xb3_in; xb5_in <= xb4_in; xb6_in <= xb5_in; xb7_in <= xb6_in;
       end
   else if (en_dct2d_reg == 1'b0)
       begin
       xb0_in <= 11'b0; xb1_in <= 11'b0; xb2_in <= 11'b0; xb3_in <= 11'b0;
       xb4_in <= 11'b0; xb5_in <= 11'b0; xb6_in <= 11'b0; xb7_in <= 11'b0;
       end
   end

/* register inputs, inputs read in every eighth clk*/

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       xb0_reg <= 12'b0; xb1_reg <= 12'b0; xb2_reg <= 12'b0; xb3_reg <= 12'b0;
       xb4_reg <= 12'b0; xb5_reg <= 12'b0; xb6_reg <= 12'b0; xb7_reg <= 12'b0;
       end
   else if (cntr8 == 4'b1000)
       begin
       xb0_reg <= {xb0_in[10],xb0_in}; xb1_reg <= {xb1_in[10],xb1_in}; 
       xb2_reg <= {xb2_in[10],xb2_in}; xb3_reg <= {xb3_in[10],xb3_in};
       xb4_reg <= {xb4_in[10],xb4_in}; xb5_reg <= {xb5_in[10],xb5_in}; 
       xb6_reg <= {xb6_in[10],xb6_in}; xb7_reg <= {xb7_in[10],xb7_in};
       end
   end

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       toggleB <= 1'b0;
       end
   else 
       begin 
       toggleB <= ~toggleB;
       end
   end

/* adder / subtractor block */

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       add_sub1b <= 12'b0; add_sub2b <= 12'b0; add_sub3b <= 12'b0; add_sub4b <= 12'b0;
       end
   else
       begin
	       if (toggleB == 1'b1)
	          begin
            add_sub1b <= (xb0_reg + xb7_reg); add_sub2b <= (xb1_reg + xb6_reg);
            add_sub3b <= (xb2_reg + xb5_reg); add_sub4b <= (xb3_reg + xb4_reg);
            end
	       else if (toggleB == 1'b0)
	          begin
	          add_sub1b <= (xb7_reg - xb0_reg); add_sub2b <= (xb6_reg - xb1_reg);
            add_sub3b <= (xb5_reg - xb2_reg); add_sub4b <= (xb4_reg - xb3_reg);
	          end
       end
   end

always @ (posedge RST or posedge CLK)
begin
    if (RST)
       begin  
         addsub1b_comp <= 11'b0; save_sign1b <= 1'b0;
       end
    else 
       begin
       case (add_sub1b[11])
       1'b0: begin 
              addsub1b_comp <= add_sub1b; save_sign1b <= 1'b0; 
              end
       1'b1: begin 
              addsub1b_comp <= (-add_sub1b) ; save_sign1b <= 1'b1; 
              end 
       endcase
       end
end

always @ (posedge RST or posedge CLK)
begin
    if (RST)
       begin  
         addsub2b_comp <= 11'b0; save_sign2b <= 1'b0;
       end
    else 
       begin
       case (add_sub2b[11])
       1'b0: begin 
              addsub2b_comp <= add_sub2b; save_sign2b <= 1'b0; 
              end
       1'b1: begin 
              addsub2b_comp <= (-add_sub2b) ; save_sign2b <= 1'b1; 
              end 
       endcase
       end
end

always @ (posedge RST or posedge CLK)
begin
    if (RST)
       begin  
         addsub3b_comp <= 11'b0; save_sign3b <= 1'b0;
       end
    else 
       begin
       case (add_sub3b[11])
       1'b0: begin 
              addsub3b_comp <= add_sub3b; save_sign3b <= 1'b0; 
              end
       1'b1: begin 
              addsub3b_comp <= (-add_sub3b) ; save_sign3b <= 1'b1; 
              end 
       endcase
       end
end

always @ (posedge RST or posedge CLK)
begin
    if (RST)
       begin  
         addsub4b_comp <= 11'b0; save_sign4b <= 1'b0;
       end
    else 
       begin
       case (add_sub4b[11])
       1'b0: begin 
              addsub4b_comp <= add_sub4b; save_sign4b <= 1'b0; 
              end
       1'b1: begin 
              addsub4b_comp <= (-add_sub4b) ; save_sign4b <= 1'b1; 
              end 
       endcase
       end
end

     assign p1b_all = addsub1b_comp * memory1a[6:0];
     assign p2b_all = addsub2b_comp * memory2a[6:0];
     assign p3b_all = addsub3b_comp * memory3a[6:0];
     assign p4b_all = addsub4b_comp * memory4a[6:0];

/* The following instantiation can be used while targetting Virtex2 */
//MULT18X18 mult1b (.A({9'b0,addsub1b_comp}), .B({11'b0,memory1a[6:0]}), .P(p1b_all));
//MULT18X18 mult2b (.A({9'b0,addsub2b_comp}), .B({11'b0,memory2a[6:0]}), .P(p2b_all));
//MULT18X18 mult3b (.A({9'b0,addsub3b_comp}), .B({11'b0,memory3a[6:0]}), .P(p3b_all));
//MULT18X18 mult4b (.A({9'b0,addsub4b_comp}), .B({11'b0,memory4a[6:0]}), .P(p4b_all));

always @ (posedge RST or posedge CLK)
  begin
    if (RST)
      begin
        p1b <= 20'b0; p2b <= 20'b0; p3b <= 20'b0; p4b <= 20'b0; 
      end
    else if (i_wait == 2'b00)
      begin
  
        
        p1b <= (save_sign1b ^ memory1a[7]) ? (-p1b_all[17:0]) :(p1b_all[17:0]);
        p2b <= (save_sign2b ^ memory2a[7]) ? (-p2b_all[17:0]) :(p2b_all[17:0]);
        p3b <= (save_sign3b ^ memory3a[7]) ? (-p3b_all[17:0]) :(p3b_all[17:0]);
        p4b <= (save_sign4b ^ memory4a[7]) ? (-p4b_all[17:0]) :(p4b_all[17:0]);
        end
  end
/*always @ (posedge RST or posedge CLK)
  begin
    if (RST)
      begin
        p1b <= 16'b0; p2b <= 16'b0; p3b <= 16'b0; p4b <= 16'b0; //indexj<= 7;
      end
    else if (i_wait == 2'b00)
      begin
        p1b <= (save_sign1b ^ memory1a[7]) ? (-addsub1b_comp * memory1a[6:0]) :(addsub1b_comp * memory1a[6:0]);
        p2b <= (save_sign2b ^ memory2a[7]) ? (-addsub2b_comp * memory2a[6:0]) :(addsub2b_comp * memory2a[6:0]);
        p3b <= (save_sign3b ^ memory3a[7]) ? (-addsub3b_comp * memory3a[6:0]) :(addsub3b_comp * memory3a[6:0]);
        p4b <= (save_sign4b ^ memory4a[7]) ? (-addsub4b_comp * memory4a[6:0]) :(addsub4b_comp * memory4a[6:0]);
      end
  end

*/
/* The above if else statement used to get the add_sub signals can also be implemented using  the adsu16 library element as follows */

//ADSU16 adsu16_5 (.A({8'b0,xb0_reg}), .B({8'b0,xb7_reg}), .ADD(toggleB), .CI(1'b0), .S(add_sub1b), .OFL(open), .CO(open));
//ADSU16 adsu16_6 (.A({8'b0,xb1_reg}), .B({8'b0,xb6_reg}), .ADD(toggleB), .CI(1'b0), .S(add_sub2b), .OFL(open), .CO(open));
//ADSU16 adsu16_7 (.A({8'b0,xb2_reg}), .B({8'b0,xb5_reg}), .ADD(toggleB), .CI(1'b0), .S(add_sub3b), .OFL(open), .CO(open));
//ADSU16 adsu16_8 (.A({8'b0,xb3_reg}), .B({8'b0,xb4_reg}), .ADD(toggleB), .CI(1'b0), .S(add_sub4b), .OFL(open), .CO(open));

/* multiply the outputs of the add/sub block with the 8 sets of stored coefficients */

/* Final adder. Adding the ouputs of the 4 multipliers */

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       dct2d_int1 <= 20'b0; dct2d_int2 <= 20'b0; dct_2d_int <= 20'b0;
       end
   else
       begin
       dct2d_int1 <= (p1b + p2b);
       dct2d_int2 <= (p3b + p4b);
       dct_2d_int <= (dct2d_int1 + dct2d_int2);
       end
   end

assign dct_2d_rnd = dct_2d_int[19:8];
assign dct_2d = dct_2d_int[7] ? (dct_2d_rnd + 1'b1) : dct_2d_rnd;

/* The first 1D-DCT output becomes valid after 14 +64 clk cycles. For the first 
2D-DCT output to be valid it takes 78 + 1clk to write into the ram + 1clk to 
write out of the ram + 8 clks to shift in the 1D-DCT values + 1clk to register 
the 1D-DCT values + 1clk to add/sub + 1clk to take compliment + 1 clk for 
multiplying +  2clks to add product. So the 2D-DCT output will be valid 
at the 94th clk. rdy_out goes high at 93rd clk so that the first data is valid
for the next block*/

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       cntr92 <= 8'b0;
       end
   else if (cntr92 < 8'b1011110)
       begin
       cntr92 <= cntr92 + 1;
       end
   else 
       begin
       cntr92 <= cntr92;
       end
   end

assign rdy_out = (cntr92 == 8'b1011110) ? 1'b1 : 1'b0;

endmodule
//module ADSU8 (A, B, ADD,CI,S,OFL,CO); // synthesis syn_black_box
/*input[7:0]  A,B;
input       ADD,CI;
output[7:0] S;
output      OFL,CO;
endmodule*/

//module MULT18X18 (A, B, P); // synthesis syn_black_box
/*input[17:0]  A;
input[17:0]  B;
output[35:0] P;
endmodule*/