dct.v

用verilog语言实现DCT编解码 附有DCT的说明

       end
   else  if (i_wait != 2'b00)
      begin
      i_wait  <= i_wait - 1;
      end
   else
      begin
      i_wait  <= 2'b00;
      end
   end

// First valid add_sub appears at the 10th clk (8 clks for shifting inputs,
// 9th clk for registering shifted input and 10th clk for add_sub
// to synchronize the i value to the add_sub value, i value is incremented
// only after 10 clks using i_wait
/* sign and magnitude separated here. magnitude of 9 bits is stored in *comp */

always @ (posedge RST or posedge CLK)
begin
    if (RST)
       begin  
         addsub1a_comp <= 9'b0; save_sign1a <= 1'b0;
       end
    else 
       begin
       case (add_sub1a[9])
       1'b0: begin 
              addsub1a_comp <= add_sub1a; save_sign1a <= 1'b0; 
              end
       1'b1: begin 
              addsub1a_comp <= (-add_sub1a) ; save_sign1a <= 1'b1; 
              end 
       endcase
       end
end

always @ (posedge RST or posedge CLK)
begin
    if (RST)
       begin  
         addsub2a_comp <= 9'b0; save_sign2a <= 1'b0;
       end
    else 
       begin
       case (add_sub2a[9])
       1'b0: begin 
              addsub2a_comp <= add_sub2a; save_sign2a <= 1'b0;
              end
       1'b1: begin 
              addsub2a_comp <= (-add_sub2a) ; save_sign2a <= 1'b1; 
              end 
       endcase
       end
end

always @ (posedge RST or posedge CLK)
begin
    if (RST)
       begin  
         addsub3a_comp <= 9'b0; save_sign3a <= 1'b0; 
       end
    else 
       begin
       case (add_sub3a[9])
       1'b0: begin 
              addsub3a_comp <= add_sub3a; save_sign3a <= 1'b0; 
              end
       1'b1: begin 
              addsub3a_comp <= (-add_sub3a); save_sign3a <= 1'b1; 
              end 
       endcase
       end
end

always @ (posedge RST or posedge CLK)
begin
    if (RST)
       begin  
         addsub4a_comp <= 9'b0; save_sign4a <= 1'b0; 
       end
    else 
       begin
       case (add_sub4a[9])
       1'b0: begin 
              addsub4a_comp <= add_sub4a; save_sign4a <= 1'b0; 
              end
       1'b1: begin 
              addsub4a_comp <= (-add_sub4a); save_sign4a <= 1'b1; 
              end 
       endcase
       end
end

     assign p1a_all = addsub1a_comp * memory1a[6:0];/* 9 bits * 7 bits = 16 bits*/
     assign p2a_all = addsub2a_comp * memory2a[6:0];
     assign p3a_all = addsub3a_comp * memory3a[6:0];
     assign p4a_all = addsub4a_comp * memory4a[6:0];

/* The following instantiation can be used while targetting Virtex2 */
//MULT18X18 mult1a (.A({9'b0,addsub1a_comp}), .B({11'b0,memory1a[6:0]}), .P(p1a_all));
//MULT18X18 mult2a (.A({9'b0,addsub2a_comp}), .B({11'b0,memory2a[6:0]}), .P(p2a_all));
//MULT18X18 mult3a (.A({9'b0,addsub3a_comp}), .B({11'b0,memory3a[6:0]}), .P(p3a_all));
//MULT18X18 mult4a (.A({9'b0,addsub4a_comp}), .B({11'b0,memory4a[6:0]}), .P(p4a_all));

always @ (posedge RST or posedge CLK)
  begin
    if (RST)
      begin
        p1a <= 18'b0; p2a <= 18'b0; p3a <= 18'b0; p4a <= 18'b0; indexi<= 7;
      end /* p*a is extended to one more bit to take into acoount the sign */
    else if (i_wait == 2'b00)
      begin
   
        
        p1a <= (save_sign1a ^ memory1a[7]) ? (-p1a_all[15:0]) :(p1a_all[15:0]);
        p2a <= (save_sign2a ^ memory2a[7]) ? (-p2a_all[15:0]) :(p2a_all[15:0]);
        p3a <= (save_sign3a ^ memory3a[7]) ? (-p3a_all[15:0]) :(p3a_all[15:0]);
        p4a <= (save_sign4a ^ memory4a[7]) ? (-p4a_all[15:0]) :(p4a_all[15:0]);
        

        if (indexi == 7)
          indexi <= 0;
        else
          indexi <= indexi + 1;
        end
  end


/*always @ (posedge RST or posedge CLK)
  begin
    if (RST)
      begin
        p1a <= 19'b0; p2a <= 19'b0; p3a <= 19'b0; p4a <= 19'b0; indexi<= 7;
      end
    else if (i_wait == 2'b00)
      begin
        p1a <= (save_sign1a ^ memory1a[7]) ? (-addsub1a_comp * memory1a[6:0]) :(addsub1a_comp * memory1a[6:0]);
        p2a <= (save_sign2a ^ memory2a[7]) ? (-addsub2a_comp * memory2a[6:0]) :(addsub2a_comp * memory2a[6:0]);
        p3a <= (save_sign3a ^ memory3a[7]) ? (-addsub3a_comp * memory3a[6:0]) :(addsub3a_comp * memory3a[6:0]);
        p4a <= (save_sign4a ^ memory4a[7]) ? (-addsub4a_comp * memory4a[6:0]) :(addsub4a_comp * memory4a[6:0]);
        if (indexi == 7)
          indexi <= 0;
        else
          indexi <= indexi + 1;
      end
  end*/

/* Final adder. Adding the ouputs of the 4 multipliers */

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       z_out_int1 <= 19'b0; z_out_int2 <= 19'b0; z_out_int <= 19'b0;
       end
   else
       begin
       z_out_int1 <= (p1a + p2a);
       z_out_int2 <= (p3a + p4a);
       z_out_int <= (z_out_int1 + z_out_int2);
       end
   end

// rounding of the value

assign z_out_rnd = z_out_int[7] ? (z_out_int[18:8] + 1'b1) : z_out_int[18:8];

/* 1 sign bit, 11 data bit */
assign z_out = z_out_rnd;

/* 1D-DCT END */

/* tranpose memory to store intermediate Z coeeficients */
/* store the 64 coeeficients in the first 64 locations of the RAM */
/* first valid adder output is at the 15th clk. (input reg + 8 bit SR + add_sub + comp. Signal + reg prod 
+ 2 partial prod adds) So the RAM is enabled at the 15th clk)*/

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       cntr12 <= 4'b0;
       end
   else
       begin
       cntr12 <= cntr12 + 1;
       end
   end

/* enable RAM at the 14th clk after RST goes inactive */

assign en_ram1 = RST ? 1'b0 : (cntr12== 4'b1101) ? 1'b1 : en_ram1;

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
	   en_ram1reg <= 1'b0;
       end
   else
       begin
       en_ram1reg <= en_ram1 ;
       end
   end

/* After the RAM is enabled, data is written into the RAM1 for 64 clk cycles. Data is written in into
each consecutive location . After 64 locations are written into, RAM1 goes into read mode and RAM2 goes into
write mode. The cycle then repeats.
For either RAM, data is written into each consecutive location. However , data is read in a different order. If data
is assumed to be written in each row at a time, in an 8x8 matrix, data is read each column at a time. ie., after
the first data is read out, every eight data is read out . Then the 2nd data is read out followed be every 8th.

the write is as follows:
1w(ram_locn1) 2w(ram_locn2) 3w(ram_locn3) 4w(ram_locn4) 5w(ram_locn5) 6w(ram_locn6) 7w(ram_locn7) 8w(ram_locn8)
9w(ram_locn9) 10w(ram_locn10) 11w(ram_locn11) 12w(ram_locn12) 13w(ram_locn13) 14w(ram_locn14) 15w(ram_locn15) 16w(ram_locn16)
..................
57w(ram_locn57) 58w(ram_locn58) 59w(ram_locn59) 60w(ram_locn60) 61w(ram_locn61) 62w(ram_locn62) 63w(ram_locn63) 64w(ram_locn64)

the read is as follows:
1r(ram_locn1)  9r(ram_locn2) . . . 57r(ram_locn8)
2r(ram_locn9) 10r(ram_locn10) . . . 58r(ram_locn16) 
3r(ram_locn17) 11r(ram_locn18) . . . 59r(ram_locn24)
4r(ram_locn25) 12r(ram_locn26) . . . 60r(ram_locn32)
5r(ram_locn33) 13r(ram_locn34) . . . 61r(ram_locn40)
6r(ram_locn41) 14r(ram_locn42) . . . 62r(ram_locn48)
7r(ram_locn49) 15r(ram_locn50) . . . 63r(ram_locn56)
8r(ram_locn57) 16r(ram_locn58) . . . 64r(ram_locn64)

where "xw" is the xth write and "ram_locnx" is the xth ram location and "xr" is the xth read. Reading 
is advanced by the read counter rd_cntr, nd writing by the write counter wr_cntr. */


always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
	   rd_cntr[5:3] <= 3'b111;
       end
   else
       begin 
	   if (en_ram1reg == 1'b1)
	       rd_cntr[5:3] <= rd_cntr[5:3] + 1;
	   end
   end

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
	   rd_cntr[2:0] <= 3'b111;
       end
   else
       begin 
	   if (en_ram1reg == 1'b1 && rd_cntr[5:3] == 3'b111)
	       rd_cntr[2:0] <= rd_cntr[2:0] + 1;
       end
   end

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
	   rd_cntr[6] <= 1'b1;
       end
   else
       begin 
       if (en_ram1reg == 1'b1 && rd_cntr[5:0] == 6'b111111)
          rd_cntr[6] <= ~rd_cntr[6];
       end
   end


always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       wr_cntr <= 7'b1111111;
       end
   else begin
       if (en_ram1reg == 1'b1)
          wr_cntr <= wr_cntr + 1;
	   else 
	      wr_cntr <= 7'b0;
       end
   end


initial
begin
ram2_mem[0] <= 16'b0; ram2_mem[1] <= 16'b0; ram2_mem[2] <= 16'b0; ram2_mem[3] <= 16'b0; ram2_mem[4] <= 16'b0;
ram2_mem[5] <= 16'b0; ram2_mem[6] <= 16'b0; ram2_mem[7] <= 16'b0; ram2_mem[8] <= 16'b0; ram2_mem[9] <= 16'b0;
ram2_mem[10] <= 16'b0; ram2_mem[11] <= 16'b0; ram2_mem[12] <= 16'b0; ram2_mem[13] <= 16'b0; ram2_mem[14] <= 16'b0;
ram2_mem[15] <= 16'b0; ram2_mem[16] <= 16'b0; ram2_mem[17] <= 16'b0; ram2_mem[18] <= 16'b0; ram2_mem[19] <= 16'b0;
ram2_mem[20] <= 16'b0; ram2_mem[21] <= 16'b0; ram2_mem[22] <= 16'b0; ram2_mem[23] <= 16'b0; ram2_mem[24] <= 16'b0;
ram2_mem[25] <= 16'b0; ram2_mem[26] <= 16'b0; ram2_mem[27] <= 16'b0; ram2_mem[28] <= 16'b0; ram2_mem[29] <= 16'b0;
ram2_mem[30] <= 16'b0; ram2_mem[31] <= 16'b0; ram2_mem[32] <= 16'b0; ram2_mem[33] <= 16'b0; ram2_mem[34] <= 16'b0;
ram2_mem[35] <= 16'b0; ram2_mem[36] <= 16'b0; ram2_mem[37] <= 16'b0; ram2_mem[38] <= 16'b0; ram2_mem[39] <= 16'b0;
ram2_mem[40] <= 16'b0; ram2_mem[41] <= 16'b0; ram2_mem[42] <= 16'b0; ram2_mem[43] <= 16'b0; ram2_mem[44] <= 16'b0;
ram2_mem[45] <= 16'b0; ram2_mem[46] <= 16'b0; ram2_mem[47] <= 16'b0; ram2_mem[48] <= 16'b0; ram2_mem[49] <= 16'b0;
ram2_mem[50] <= 16'b0; ram2_mem[51] <= 16'b0; ram2_mem[52] <= 16'b0; ram2_mem[53] <= 16'b0; ram2_mem[54] <= 16'b0;
ram2_mem[55] <= 16'b0; ram2_mem[56] <= 16'b0; ram2_mem[57] <= 16'b0; ram2_mem[58] <= 16'b0; ram2_mem[59] <= 16'b0;
ram2_mem[60] <= 16'b0; ram2_mem[61] <= 16'b0; ram2_mem[62] <= 16'b0; ram2_mem[63] <= 16'b0;
 
ram1_mem[0] <= 16'b0; ram1_mem[1] <= 16'b0; ram1_mem[2] <= 16'b0; ram1_mem[3] <= 16'b0; ram1_mem[4] <= 16'b0;
ram1_mem[5] <= 16'b0; ram1_mem[6] <= 16'b0; ram1_mem[7] <= 16'b0; ram1_mem[8] <= 16'b0; ram1_mem[9] <= 16'b0;
ram1_mem[10] <= 16'b0; ram1_mem[11] <= 16'b0; ram1_mem[12] <= 16'b0; ram1_mem[13] <= 16'b0; ram1_mem[14] <= 16'b0;
ram1_mem[15] <= 16'b0; ram1_mem[16] <= 16'b0; ram1_mem[17] <= 16'b0; ram1_mem[18] <= 16'b0; ram1_mem[19] <= 16'b0;
ram1_mem[20] <= 16'b0; ram1_mem[21] <= 16'b0; ram1_mem[22] <= 16'b0; ram1_mem[23] <= 16'b0; ram1_mem[24] <= 16'b0;
ram1_mem[25] <= 16'b0; ram1_mem[26] <= 16'b0; ram1_mem[27] <= 16'b0; ram1_mem[28] <= 16'b0; ram1_mem[29] <= 16'b0;
ram1_mem[30] <= 16'b0; ram1_mem[31] <= 16'b0; ram1_mem[32] <= 16'b0; ram1_mem[33] <= 16'b0; ram1_mem[34] <= 16'b0;
ram1_mem[35] <= 16'b0; ram1_mem[36] <= 16'b0; ram1_mem[37] <= 16'b0; ram1_mem[38] <= 16'b0; ram1_mem[39] <= 16'b0;
ram1_mem[40] <= 16'b0; ram1_mem[41] <= 16'b0; ram1_mem[42] <= 16'b0; ram1_mem[43] <= 16'b0; ram1_mem[44] <= 16'b0;
ram1_mem[45] <= 16'b0; ram1_mem[46] <= 16'b0; ram1_mem[47] <= 16'b0; ram1_mem[48] <= 16'b0; ram1_mem[49] <= 16'b0;
ram1_mem[50] <= 16'b0; ram1_mem[51] <= 16'b0; ram1_mem[52] <= 16'b0; ram1_mem[53] <= 16'b0; ram1_mem[54] <= 16'b0;
ram1_mem[55] <= 16'b0; ram1_mem[56] <= 16'b0; ram1_mem[57] <= 16'b0; ram1_mem[58] <= 16'b0; ram1_mem[59] <= 16'b0;
ram1_mem[60] <= 16'b0; ram1_mem[61] <= 16'b0; ram1_mem[62] <= 16'b0; ram1_mem[63] <= 16'b0;