cla8.v

一个超前进位加法器的Verilog实现

`timescale 1ns/1ns
`define DELAY 0
module add8(a,b,cin,s,cout);
parameter S1 =  8;
parameter S0 = 4;
input [S1-1:0] a,b;
input cin;
output [S1-1:0] s;
output cout;
wire [S1-1:0] p,g;
wire [S0-1:0] gP,gG;
wire [S1-1:0] C;
wire [S0-1:0] CC;

pg4 U00(.a(a[S0-1:0]),
	.b(b[S0-1:0]),
	.p(p[S0-1:0]),
	.g(g[S0-1:0]));
pg4 U01(.a(a[S1-1:S0]),
	.b(b[S1-1:S0]),
	.p(p[S1-1:S0]),
	.g(g[S1-1:S0]));
cla4 U10(.p(p[S0-1:0]),
	.g(g[S0-1:0]),
	.cin(cin),
	.P(gP[0]),
	.G(gG[0]),
	.C(C[S0-1:0]));
cla4 U11(.p(p[S1-1:S0]),
	.g(g[S1-1:S0]),
	.cin(CC[0]),
	.P(gP[1]),
	.G(gG[1]),
	.C(C[S1-1:S0]));
cla4 U2(.p(gP),
	.g(gG),
	.cin(cin),
	.P(gPP),
	.G(gGG),
	.C(CC[S0-1:0]));
sum4 U30(.a(a[S0-1:0]),
	.b(b[S0-1:0]),
	.c({C[S0-2:0],cin}),
	.s(s[S0-1:0]));
sum4 U31(.a(a[S1-1:S0]),
	.b(b[S1-1:S0]),
	.c({C[S1-2:S0],CC[0]}),
	.s(s[S1-1:S0]));
assign gP[3:2] = 2'b11;
assign gG[3:2] = 2'b00;
assign #DELAY cout = CC[3];
endmodule

module cla4(p,g,cin,P,G,C);
input [3:0] p,g;
input cin;
output P,G;
output [3:0] C;
wire P0,P1,P2,G0,G1,G2;
assign #DELAY P0 = p[0];
assign #DELAY P1 = p[0]&p[1];
assign #DELAY P2 = p[0]&p[1]&p[2];
assign #DELAY P = &p;
assign #DELAY G0 = g[0];
assign #DELAY G1 = g[0]&p[1]|g[1];
assign #DELAY G2 = g[0]&p[1]&p[2]|g[1]&p[2]|g[2];
assign #DELAY G = g[0]&(&p[3:1])|g[1]&(&p[3:2])|g[2]&p[3]|g[3];
assign #DELAY C[0] = cin&P0|G0;
assign #DELAY C[1] = cin&P1|G1;
assign #DELAY C[2] = cin&P2|G2;
assign #DELAY C[3] = cin&P|G;
endmodule

module sum4(a,b,c,s);
input [3:0] a,b,c;
output [3:0] s;
assign #DELAY s = a^b^c;
endmodule

module pg4(a,b,p,g);
input [3:0] a,b;
output [3:0] p,g;
assign #DELAY p = a|b;
assign #DELAY g = a&b;
endmodule