_primary.vhd

来自「一个超前进位加法器的Verilog实现」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity add8 is
    generic(
        S1              : integer := 8;
        S0              : integer := 4
    );
    port(
        a               : in     vl_logic_vector;
        b               : in     vl_logic_vector;
        cin             : in     vl_logic;
        s               : out    vl_logic_vector;
        cout            : out    vl_logic
    );
end add8;