_primary.vhd

来自「一个超前进位加法器的Verilog实现」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity cla4 is
    port(
        p               : in     vl_logic_vector(3 downto 0);
        g               : in     vl_logic_vector(3 downto 0);
        cin             : in     vl_logic;
        \P\             : out    vl_logic;
        \G\             : out    vl_logic;
        C               : out    vl_logic_vector(3 downto 0)
    );
end cla4;