📄 transcript

📁 一个超前进位加法器的Verilog实现
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# Compile of CLA8.v failed with 1 errors.
# Compile of CLA8.v failed with 1 errors.
# Compile of CLA8.v failed with 1 errors.
# Compile of CLA8.v failed with 1 errors.
# Compile of CLA8.v failed with 1 errors.
# Compile of CLA8.v failed with 1 errors.
# Compile of CLA8.v failed with 1 errors.
# Compile of CLA8.v failed with 1 errors.
# Compile of CLA8.v failed with 1 errors.
# Compile of CLA8.v failed with 1 errors.
# Compile of CLA8.v failed with 1 errors.
# Compile of CLA8.v was successful.
# Compile of add8_tb.v was successful.
vism work.add8_tb
# invalid command name "vism"
vsim work.add8_tb
# vsim work.add8_tb 
# Loading work.add8_tb
# Loading work.add8
# ** Warning: (vsim-3010) [TSCALE] - Module 'add8' has a `timescale directive in effect, but previous modules do not.
#         Region: /add8_tb/T0
# Loading work.pg4
# Loading work.cla4
# Loading work.sum4
# ** Warning: (vsim-3017) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Too few port connections. Expected 5, found 3.
#         Region: /add8_tb/T0
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 'cout'.
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 's'.
# ** Warning: (vsim-3015) E:/CGT/EDA/Verilog/CLA8/CLA8.v(33): [PCDPC] - Port size (4 or 4) does not match connection size (8) for port 'p'.
#         Region: /add8_tb/T0/U11
# ** Warning: (vsim-3015) E:/CGT/EDA/Verilog/CLA8/CLA8.v(33): [PCDPC] - Port size (4 or 4) does not match connection size (8) for port 'g'.
#         Region: /add8_tb/T0/U11
# Compile of CLA8.v was successful.
quit -sm
# unknown switch: -sm
quit -sim
vsim work.add8_tb
# vsim work.add8_tb 
# Loading work.add8_tb
# Loading work.add8
# ** Warning: (vsim-3010) [TSCALE] - Module 'add8' has a `timescale directive in effect, but previous modules do not.
#         Region: /add8_tb/T0
# Loading work.pg4
# Loading work.cla4
# Loading work.sum4
# ** Warning: (vsim-3017) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Too few port connections. Expected 5, found 3.
#         Region: /add8_tb/T0
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 'cout'.
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 's'.
view w
# .wave
add w -r /*
run
# Compile of CLA8.v was successful.
restart
# Loading work.add8
# ** Warning: (vsim-3010) [TSCALE] - Module 'add8' has a `timescale directive in effect, but previous modules do not.
#         Region: /add8_tb/T0
# Loading work.pg4
# Loading work.cla4
# Loading work.sum4
# ** Warning: (vsim-3017) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Too few port connections. Expected 5, found 3.
#         Region: /add8_tb/T0
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 'cout'.
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 's'.
run
# Compile of CLA8.v was successful.
restart
# Loading work.add8
# ** Warning: (vsim-3010) [TSCALE] - Module 'add8' has a `timescale directive in effect, but previous modules do not.
#         Region: /add8_tb/T0
# Loading work.pg4
# Loading work.cla4
# Loading work.sum4
# ** Warning: (vsim-3017) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Too few port connections. Expected 5, found 3.
#         Region: /add8_tb/T0
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 'cout'.
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 's'.
# Warning in wave window restart:  No objects found matching "/add8_tb/T0/U10/P3" 
# Warning in wave window restart:  No objects found matching "/add8_tb/T0/U10/G3" 
# Warning in wave window restart:  No objects found matching "/add8_tb/T0/U11/P3" 
# Warning in wave window restart:  No objects found matching "/add8_tb/T0/U11/G3" 
# Warning in wave window restart:  No objects found matching "/add8_tb/T0/U2/P3" 
# Warning in wave window restart:  No objects found matching "/add8_tb/T0/U2/G3" 
run
# Compile of add8_tb.v was successful.
restart
# Loading work.add8_tb
# ** Warning: (vsim-3010) [TSCALE] - Module 'add8' has a `timescale directive in effect, but previous modules do not.
#         Region: /add8_tb/T0
# ** Warning: (vsim-3017) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Too few port connections. Expected 5, found 3.
#         Region: /add8_tb/T0
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 'cout'.
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 's'.
run
# Compile of CLA8.v was successful.
restart
# Loading work.add8
# ** Warning: (vsim-3010) [TSCALE] - Module 'add8' has a `timescale directive in effect, but previous modules do not.
#         Region: /add8_tb/T0
# Loading work.pg4
# Loading work.cla4
# Loading work.sum4
# ** Warning: (vsim-3017) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Too few port connections. Expected 5, found 3.
#         Region: /add8_tb/T0
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 'cout'.
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 's'.
run
# Compile of add8_tb.v was successful.
restart
# Loading work.add8_tb
# ** Warning: (vsim-3010) [TSCALE] - Module 'add8' has a `timescale directive in effect, but previous modules do not.
#         Region: /add8_tb/T0
# ** Warning: (vsim-3017) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Too few port connections. Expected 5, found 3.
#         Region: /add8_tb/T0
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 'cout'.
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 's'.
run
# Compile of add8_tb.v was successful.
restart
# Loading work.add8_tb
# ** Warning: (vsim-3010) [TSCALE] - Module 'add8' has a `timescale directive in effect, but previous modules do not.
#         Region: /add8_tb/T0
# ** Warning: (vsim-3017) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Too few port connections. Expected 5, found 3.
#         Region: /add8_tb/T0
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 'cout'.
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 's'.
run
# Compile of add8_tb.v was successful.
restart
# Loading work.add8_tb
# ** Warning: (vsim-3010) [TSCALE] - Module 'add8' has a `timescale directive in effect, but previous modules do not.
#         Region: /add8_tb/T0
# ** Warning: (vsim-3017) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Too few port connections. Expected 5, found 3.
#         Region: /add8_tb/T0
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 'cout'.
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 's'.
run
# Compile of CLA8.v was successful.
restart
# Loading work.add8
# ** Warning: (vsim-3010) [TSCALE] - Module 'add8' has a `timescale directive in effect, but previous modules do not.
#         Region: /add8_tb/T0
# Loading work.pg4
# Loading work.cla4
# Loading work.sum4
# ** Warning: (vsim-3017) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Too few port connections. Expected 5, found 3.
#         Region: /add8_tb/T0
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 'cout'.
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 's'.
run
# Compile of add8_tb.v was successful.
restart
# Loading work.add8_tb
# ** Warning: (vsim-3010) [TSCALE] - Module 'add8' has a `timescale directive in effect, but previous modules do not.
#         Region: /add8_tb/T0
# ** Warning: (vsim-3017) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Too few port connections. Expected 5, found 3.
#         Region: /add8_tb/T0
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 'cout'.
# ** Warning: (vsim-3722) E:/CGT/EDA/Verilog/CLA8/add8_tb.v(7): [TFMPC] - Missing connection for port 's'.
run
quit -sim
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