add8_tb.v

一个超前进位加法器的Verilog实现

module add8_tb();
reg [7:0]ta,tb;
reg tcin;

add8 T0(.a(ta),
	.b(tb),
	.cin(tcin));
initial
begin
	ta = 5;
	tb = 5;
	tcin = 1;
	#10;
	ta = 120;
	tb = 100;
	tcin = 1;
	#100;
	$display("the end");
end
endmodule