test.v

来自「用ＭＡＴＬＡＢ产生各种时钟信号」· Verilog 代码 · 共 31 行

`timescale 1ns/100ps
module  top();

reg clk  ;
reg rstn ;

initial
begin
    clk  = 0 ;
    rstn = 0 ;
    #1000    ;
    rstn = 1 ;
    #10000000;
    $finish  ;
end

always #5 clk = !clk;

    clk_gen clk_gen (.clk(clk), .rstn(rstn), .clk_o(clk_1));

    clk_div clk_div (.clk(clk), .rstn(rstn), .clk_o(clk_2)); 

initial
begin
    $fsdbDumpvars(0, top);
    $fsdbDumpfile("top.fsdb");
end
    
endmodule