clk_div.v

来自「用ＭＡＴＬＡＢ产生各种时钟信号」· Verilog 代码 · 共 64 行

//////////////////////////////////
//  Clock Divider by Odd Number //
//////////////////////////////////

module  clk_div ( 
                 clk   ,
                 rstn  ,
                 clk_o
                 ); 

input  clk   ;
input  rstn  ;
output clk_o ;

parameter  N = 9 ; // 3, 5, 7

// Posedge Domain 
reg       clkn_pos  ;
reg[7:0]  count_pos ;
wire      clear_pos = (count_pos == (N - 1));
wire      updat_pos = (count_pos == (N-1)/2);
always @(posedge clk or negedge rstn )
if (!rstn )
    count_pos <= #3 8'h00 ;
else if(clear_pos )    
    count_pos <= #3 8'h00 ;
else 
    count_pos <= #3 count_pos + 1'b1 ;
    
always @(posedge clk or negedge rstn )
if (!rstn )
    clkn_pos  <= #3 1'b0 ;
else if(updat_pos )
    clkn_pos  <= #3 1'b1 ;
else if(clear_pos )
    clkn_pos  <= #3 1'b0 ;         

// Negedge Domain 
reg       clkn_neg  ;
reg[7:0]  count_neg ;
wire      clear_neg = (count_neg == (N - 1));
wire      updat_neg = (count_neg == (N-1)/2);
always @(negedge clk or negedge rstn )
if (!rstn )
    count_neg <= #3 8'h00 ;
else if(clear_neg )    
    count_neg <= #3 8'h00 ;
else 
    count_neg <= #3 count_neg + 1'b1 ;
    
always @(negedge clk or negedge rstn )
if (!rstn )
    clkn_neg  <= #3 1'b0 ;
else if(updat_neg )
    clkn_neg  <= #3 1'b1 ;
else if(clear_neg )
    clkn_neg  <= #3 1'b0 ;                                   

wire  clk_o = clkn_pos | clkn_neg ;

/////////////////////////////////////////////
endmodule