_primary.vhd

来自「用ＭＡＴＬＡＢ产生各种时钟信号」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity clk_div is
    generic(
        n               : integer := 9
    );
    port(
        clk             : in     vl_logic;
        rstn            : in     vl_logic;
        clk_o           : out    vl_logic
    );
end clk_div;