m_bus.v

VERILOG五POSPHY LEVEL3电路描述

//**************************************************************************************************************************************
// +fhdr---------------------------------------------------------------------------------------------------------------
// copyright (c) 2005,xws.
// xws confidential proprietary
// --------------------------------------------------------------------------------------------------------------------
// project    : pos_phy fpga 
// file name  : m_bus.v
// directory  : 
// type       : synthesisable rtl code , verilog
// called by  : pl3_fpga_top.v
// calls to   : 
//              
//              
//              
// version    : ver1.0
// --------------------------------------------------------------------------------------------------------------------
// author     : xws
// e-mail     : [e-mail] 
// department : R&D center
// --------------------------------------------------------------------------------------------------------------------
// purpose    :  
// function   : 
// creatdate  : 2005-09-13 
// updatedate : 
// history    : 
// clock domains:   100MHz
// reset strategy:  
// see also:
// detail description: 
// --------------------------------------------------------------------------------------------------------------------
// keywords   :
// -fhdr---------------------------------------------------------------------------------------------------------------
//*************************************************************************************************************************************
`include "define.v"

module m_bus(
             //system signals
             h_reset_n,
             s_reset_n,
             sys_clk_100m,
                                   
             //signals from mpc8241 block
             mpc_csb,
             mpc_rdb,                   
             mpc_wrb,
             mpc_data,                                  
             mpc_addr,
                                                                                                                           
             //signals to pmc device(3386,5382,5381) block 
             pmc_3386_1_csb,
             pmc_3386_2_csb,
             pmc_5382_csb, 
             pmc_5381_csb,             
             //common signals
             pmc_rdb,
             pmc_wrb,
             pmc_data,
             pmc_addr,
             pmc_ale,
             
             //signals to pmc and mpc device block 
             mpc_8241_rstb,
             pmc_3386_1_rstb,
             pmc_3386_2_rstb,
             pmc_5382_rstb,
             pmc_5381_rstb,
             
             //signals to pl3 block
             header_length,
             crc_length,
             ge0_da_mac,
             ge0_sa_mac,
             ge1_da_mac,
             ge1_sa_mac,
             ge2_da_mac,
             ge2_sa_mac,
             ge3_da_mac,
             ge3_sa_mac,

             lose_pkt_cnt_0,
             lose_pkt_cnt_1,
             lose_pkt_cnt_2,
             lose_pkt_cnt_3,
             lose_pkt_cnt_4,
             lose_pkt_cnt_5,
             lose_pkt_cnt_6,
             lose_pkt_cnt_7,
             lose_pkt_cnt_8,
             lose_pkt_cnt_9,
             lose_pkt_cnt_10,
             lose_pkt_cnt_11,
             lose_pkt_cnt_12,
             lose_pkt_cnt_13,
             lose_pkt_cnt_14,
             lose_pkt_cnt_15,
                                                                                                                             
             //test signals
             test_sel,
             test_point                 
             );
                      

//system signals
input h_reset_n;
input s_reset_n;
input sys_clk_100m;
                      
//signals from mpc8241 block
input       mpc_csb;
input       mpc_rdb;                   
input       mpc_wrb;
inout [15:0]mpc_data;                                  
input [15:0]mpc_addr;
                                                                                                              
//signals to pmc device(3386,5382,5381) block 
output pmc_3386_1_csb;
output pmc_3386_2_csb;
output pmc_5382_csb;
output pmc_5381_csb;             
//common signals
output       pmc_rdb;
output       pmc_wrb;
inout  [15:0]pmc_data;
output [12:0]pmc_addr;
output       pmc_ale;

//signals to pmc and mpc device block 
output mpc_8241_rstb;
output pmc_3386_1_rstb;
output pmc_3386_2_rstb;
output pmc_5382_rstb;
output pmc_5381_rstb;

//signals to pl3 block
output header_length;
output crc_length;
output [47:0]ge0_da_mac;
output [47:0]ge0_sa_mac;
output [47:0]ge1_da_mac;
output [47:0]ge1_sa_mac;
output [47:0]ge2_da_mac;
output [47:0]ge2_sa_mac;
output [47:0]ge3_da_mac;
output [47:0]ge3_sa_mac;

input [15:0]lose_pkt_cnt_0;
input [15:0]lose_pkt_cnt_1;
input [15:0]lose_pkt_cnt_2;
input [15:0]lose_pkt_cnt_3;
input [15:0]lose_pkt_cnt_4;
input [15:0]lose_pkt_cnt_5;
input [15:0]lose_pkt_cnt_6;
input [15:0]lose_pkt_cnt_7;
input [15:0]lose_pkt_cnt_8;
input [15:0]lose_pkt_cnt_9;
input [15:0]lose_pkt_cnt_10;
input [15:0]lose_pkt_cnt_11;
input [15:0]lose_pkt_cnt_12;
input [15:0]lose_pkt_cnt_13;
input [15:0]lose_pkt_cnt_14;
input [15:0]lose_pkt_cnt_15;
                                                                                                      
//test signals
input   [7:0]test_sel;
output [31:0]test_point;            

////////////////////////////////////////////////////////
//port declaration
///////////////////////////////////////////////////////
//signals to pmc device(3386,5382,5381) block 
reg pmc_3386_1_csb;
reg pmc_3386_2_csb;
reg pmc_5382_csb;
reg pmc_5381_csb;             
//common signals
reg       pmc_rdb;
reg       pmc_wrb;
wire[15:0]pmc_data;
reg [12:0]pmc_addr;
reg       pmc_ale;

//signals to pmc and mpc device block 
reg mpc_8241_rstb;
reg pmc_3386_1_rstb;
reg pmc_3386_2_rstb;
reg pmc_5382_rstb;
reg pmc_5381_rstb;

//signals to pl3 block
reg header_length;
reg crc_length;
reg [47:0]ge0_da_mac;
reg [47:0]ge0_sa_mac;
reg [47:0]ge1_da_mac;
reg [47:0]ge1_sa_mac;
reg [47:0]ge2_da_mac;
reg [47:0]ge2_sa_mac;
reg [47:0]ge3_da_mac;
reg [47:0]ge3_sa_mac;
                                                                                                       
//test signals
reg [31:0]test_point;     
////////////////////////////////////////////////////////////////////////
//parameter define
parameter fpga_sel      = 3'b001;
parameter pmc3386_1_sel = 3'b010;
parameter pmc3386_2_sel = 3'b011;
parameter pmc5381_sel   = 3'b100;
parameter pmc5382_sel   = 3'b101;

///////////////////////////////////////////////////////////////////////
//internal register definition
///////////////////////////////////////////////////////////////////////
reg [15:0]reset_sel;
reg [15:0]header_len_sel;
reg [15:0]crc_len_sel;

reg [15:0]ge0_da_mac_0,ge0_da_mac_1,ge0_da_mac_2;
reg [15:0]ge0_sa_mac_0,ge0_sa_mac_1,ge0_sa_mac_2;

reg [15:0]ge1_da_mac_0,ge1_da_mac_1,ge1_da_mac_2;
reg [15:0]ge1_sa_mac_0,ge1_sa_mac_1,ge1_sa_mac_2;

reg [15:0]ge2_da_mac_0,ge2_da_mac_1,ge2_da_mac_2;
reg [15:0]ge2_sa_mac_0,ge2_sa_mac_1,ge2_sa_mac_2;

reg [15:0]ge3_da_mac_0,ge3_da_mac_1,ge3_da_mac_2;
reg [15:0]ge3_sa_mac_0,ge3_sa_mac_1,ge3_sa_mac_2;

reg [15:0]lose_pkt_cnt_ch0;
reg [15:0]lose_pkt_cnt_ch1;
reg [15:0]lose_pkt_cnt_ch2;
reg [15:0]lose_pkt_cnt_ch3;
reg [15:0]lose_pkt_cnt_ch4;
reg [15:0]lose_pkt_cnt_ch5;
reg [15:0]lose_pkt_cnt_ch6;
reg [15:0]lose_pkt_cnt_ch7;
reg [15:0]lose_pkt_cnt_ch8;
reg [15:0]lose_pkt_cnt_ch9;
reg [15:0]lose_pkt_cnt_ch10;
reg [15:0]lose_pkt_cnt_ch11;
reg [15:0]lose_pkt_cnt_ch12;
reg [15:0]lose_pkt_cnt_ch13;
reg [15:0]lose_pkt_cnt_ch14;
reg [15:0]lose_pkt_cnt_ch15;

//////////////////////////////////////////////////////////////////////
//***************description*************************//
//reset_sel[0]==1 ---> reset all pmc device and mpc8241
//reset_sel[1]==1 ---> mpc_8241_rstb 
//reset_sel[2]==1 ---> pmc_3386_1_rstb
//reset_sel[3]==1 ---> pmc_3386_2_rstb
//reset_sel[4]==1 ---> pmc_5381_rstb
//reset_sel[5]==1 ---> pmc_5382_rstb
//****************************************************//
//header_len_sel[0]==0 ---> 2 byte header
//header_len_sel[0]==1 ---> 3 byte header 
//crc_len_sel[0]==0 ---> 2 byte crc16
//crc_len_sel[0]==1 ---> 4 byte crc32
//***************************************************//
///////////////////////////////////////////////////////////////////////
reg fpga_csb;
reg fpga_csb_tmp;       
reg pmc_3386_1_csb_tmp; 
reg pmc_3386_2_csb_tmp; 
reg pmc_5381_csb_tmp;   
reg pmc_5382_csb_tmp;
    
reg fpga_csb_tmp_d,fpga_csb_tmp_2d;
reg pmc_3386_1_csb_tmp_d,pmc_3386_1_csb_tmp_2d;
reg pmc_3386_2_csb_tmp_d,pmc_3386_2_csb_tmp_2d;
reg pmc_5381_csb_tmp_d,pmc_5381_csb_tmp_2d;
reg pmc_5382_csb_tmp_d,pmc_5382_csb_tmp_2d;

reg       mpc_rdb_d,mpc_rdb_2d,mpc_rdb_3d;
reg       mpc_wrb_d,mpc_wrb_2d;
reg [15:0]mpc_addr_d;
reg [15:0]rd_fpga_data_tmp;
reg  [7:0]reset_time_cnt;

reg fpga_csb_d;
reg pmc_rdb_d;

wire [15:0]mpc_data;
wire [15:0]data_in_from_mpc;
wire [15:0]data_out_to_mpc;

reg pmc_wrb_d;

//wire [15:0]pmc_data;
wire [15:0]data_in_from_pmc;
reg  [15:0]data_out_to_pmc;

reg  [15:0]data_in_from_mpc_d;

reg mpc_csb_d;
    
////////////////////////////////////////////////////////////////////////////////
//test point assignment
always @(*)
begin
  if(h_reset_n)
    begin
      test_point[31:0]<=32'b0;
    end
  else if(s_reset_n)
    begin
      test_point[31:0]<=32'b0;
    end
  else
    case(test_sel[5:0])
      6'b00_0000: test_point[31:0]<={12'b0,mpc_data[15:0],mpc_wrb,mpc_rdb,mpc_csb,sys_clk_100m};
      6'b00_0001: test_point[31:0]<={12'b0,mpc_addr[15:0],mpc_wrb,mpc_rdb,mpc_csb,sys_clk_100m};
      6'b00_0010: test_point[31:0]<={11'b0,pmc_ale,pmc_data[15:0],pmc_wrb,pmc_rdb,pmc_3386_1_csb,sys_clk_100m};      
      6'b00_0011: test_point[31:0]<={14'b0,pmc_ale,pmc_addr[12:0],pmc_wrb,pmc_rdb,pmc_3386_1_csb,sys_clk_100m};
      6'b00_0100: test_point[31:0]<={11'b0,pmc_ale,pmc_data[15:0],pmc_wrb,pmc_rdb,pmc_3386_2_csb,sys_clk_100m};
      6'b00_0101: test_point[31:0]<={14'b0,pmc_ale,pmc_addr[12:0],pmc_wrb,pmc_rdb,pmc_3386_2_csb,sys_clk_100m};
      6'b00_0110: test_point[31:0]<={11'b0,pmc_ale,pmc_data[15:0],pmc_wrb,pmc_rdb,pmc_5382_csb,sys_clk_100m};
      6'b00_0111: test_point[31:0]<={14'b0,pmc_ale,pmc_addr[12:0],pmc_wrb,pmc_rdb,pmc_5382_csb,sys_clk_100m};
      6'b00_1000: test_point[31:0]<={11'b0,pmc_ale,pmc_data[15:0],pmc_wrb,pmc_rdb,pmc_5381_csb,sys_clk_100m};
      6'b00_1001: test_point[31:0]<={14'b0,pmc_ale,pmc_addr[12:0],pmc_wrb,pmc_rdb,pmc_5381_csb,sys_clk_100m};      
      default: ;
    endcase
end 

////////////////////////////////////////////////////////////////////////////////
//generate rstb 
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      mpc_8241_rstb  <=1'b0;
      pmc_3386_1_rstb<=1'b0;
      pmc_3386_2_rstb<=1'b0;
      pmc_5381_rstb  <=1'b0;
      pmc_5382_rstb  <=1'b0;       
    end
  else if(~s_reset_n)
    begin
      mpc_8241_rstb  <=1'b0;
      pmc_3386_1_rstb<=1'b0;
      pmc_3386_2_rstb<=1'b0;
      pmc_5381_rstb  <=1'b0; 
      pmc_5382_rstb  <=1'b0;
    end
  else if(reset_sel[0]==1'b1)
    begin
      mpc_8241_rstb  <=1'b0;
      pmc_3386_1_rstb<=1'b0;
      pmc_3386_2_rstb<=1'b0;
      pmc_5381_rstb  <=1'b0; 
      pmc_5382_rstb  <=1'b0;      
    end    
  else if(reset_sel[1] || reset_sel[2] || reset_sel[3] || reset_sel[4] || reset_sel[5])
    begin
      case({reset_sel[1],reset_sel[2],reset_sel[3],reset_sel[4],reset_sel[5]})
        5'b0_0001: begin    
                   mpc_8241_rstb  <=1'b1;
                   pmc_3386_1_rstb<=1'b1;
                   pmc_3386_2_rstb<=1'b1;
                   pmc_5381_rstb  <=1'b1;
                   pmc_5382_rstb  <=1'b0;                   
                 end