m_bus.v
来自「VERILOG五POSPHY LEVEL3电路描述」· Verilog 代码 · 共 1,450 行 · 第 1/4 页
V
1,450 行
5'b0_0010: begin
mpc_8241_rstb <=1'b1;
pmc_3386_1_rstb<=1'b1;
pmc_3386_2_rstb<=1'b1;
pmc_5381_rstb <=1'b0;
pmc_5382_rstb <=1'b1;
end
5'b0_0011: begin
mpc_8241_rstb <=1'b1;
pmc_3386_1_rstb<=1'b1;
pmc_3386_2_rstb<=1'b1;
pmc_5381_rstb <=1'b0;
pmc_5382_rstb <=1'b0;
end
5'b0_0100: begin
mpc_8241_rstb <=1'b1;
pmc_3386_1_rstb<=1'b1;
pmc_3386_2_rstb<=1'b0;
pmc_5381_rstb <=1'b1;
pmc_5382_rstb <=1'b1;
end
5'b0_0101: begin
mpc_8241_rstb <=1'b1;
pmc_3386_1_rstb<=1'b1;
pmc_3386_2_rstb<=1'b0;
pmc_5381_rstb <=1'b1;
pmc_5382_rstb <=1'b0;
end
5'b0_0110: begin
mpc_8241_rstb <=1'b1;
pmc_3386_1_rstb<=1'b1;
pmc_3386_2_rstb<=1'b0;
pmc_5381_rstb <=1'b0;
pmc_5382_rstb <=1'b1;
end
5'b0_0111: begin
mpc_8241_rstb <=1'b1;
pmc_3386_1_rstb<=1'b1;
pmc_3386_2_rstb<=1'b0;
pmc_5381_rstb <=1'b0;
pmc_5382_rstb <=1'b0;
end
5'b0_1000: begin
mpc_8241_rstb <=1'b1;
pmc_3386_1_rstb<=1'b0;
pmc_3386_2_rstb<=1'b1;
pmc_5381_rstb <=1'b1;
pmc_5382_rstb <=1'b1;
end
5'b0_1001: begin
mpc_8241_rstb <=1'b1;
pmc_3386_1_rstb<=1'b0;
pmc_3386_2_rstb<=1'b1;
pmc_5381_rstb <=1'b1;
pmc_5382_rstb <=1'b0;
end
5'b0_1010: begin
mpc_8241_rstb <=1'b1;
pmc_3386_1_rstb<=1'b0;
pmc_3386_2_rstb<=1'b1;
pmc_5381_rstb <=1'b0;
pmc_5382_rstb <=1'b1;
end
5'b0_1011: begin
mpc_8241_rstb <=1'b1;
pmc_3386_1_rstb<=1'b0;
pmc_3386_2_rstb<=1'b1;
pmc_5381_rstb <=1'b0;
pmc_5382_rstb <=1'b0;
end
5'b0_1100: begin
mpc_8241_rstb <=1'b1;
pmc_3386_1_rstb<=1'b0;
pmc_3386_2_rstb<=1'b0;
pmc_5381_rstb <=1'b1;
pmc_5382_rstb <=1'b1;
end
5'b0_1101: begin
mpc_8241_rstb <=1'b1;
pmc_3386_1_rstb<=1'b0;
pmc_3386_2_rstb<=1'b0;
pmc_5381_rstb <=1'b1;
pmc_5382_rstb <=1'b0;
end
5'b0_1110: begin
mpc_8241_rstb <=1'b1;
pmc_3386_1_rstb<=1'b0;
pmc_3386_2_rstb<=1'b0;
pmc_5381_rstb <=1'b0;
pmc_5382_rstb <=1'b1;
end
5'b0_1111: begin
mpc_8241_rstb <=1'b1;
pmc_3386_1_rstb<=1'b0;
pmc_3386_2_rstb<=1'b0;
pmc_5381_rstb <=1'b0;
pmc_5382_rstb <=1'b0;
end
//-----------------------------------//
5'b1_0000: begin
mpc_8241_rstb <=1'b0;
pmc_3386_1_rstb<=1'b1;
pmc_3386_2_rstb<=1'b1;
pmc_5381_rstb <=1'b1;
pmc_5382_rstb <=1'b1;
end
5'b1_0001: begin
mpc_8241_rstb <=1'b0;
pmc_3386_1_rstb<=1'b1;
pmc_3386_2_rstb<=1'b1;
pmc_5381_rstb <=1'b1;
pmc_5382_rstb <=1'b0;
end
5'b1_0010: begin
mpc_8241_rstb <=1'b0;
pmc_3386_1_rstb<=1'b1;
pmc_3386_2_rstb<=1'b1;
pmc_5381_rstb <=1'b0;
pmc_5382_rstb <=1'b1;
end
5'b1_0011: begin
mpc_8241_rstb <=1'b0;
pmc_3386_1_rstb<=1'b1;
pmc_3386_2_rstb<=1'b1;
pmc_5381_rstb <=1'b0;
pmc_5382_rstb <=1'b0;
end
5'b1_0100: begin
mpc_8241_rstb <=1'b0;
pmc_3386_1_rstb<=1'b1;
pmc_3386_2_rstb<=1'b0;
pmc_5381_rstb <=1'b1;
pmc_5382_rstb <=1'b1;
end
5'b1_0101: begin
mpc_8241_rstb <=1'b0;
pmc_3386_1_rstb<=1'b1;
pmc_3386_2_rstb<=1'b0;
pmc_5381_rstb <=1'b1;
pmc_5382_rstb <=1'b0;
end
5'b1_0110: begin
mpc_8241_rstb <=1'b0;
pmc_3386_1_rstb<=1'b1;
pmc_3386_2_rstb<=1'b0;
pmc_5381_rstb <=1'b0;
pmc_5382_rstb <=1'b1;
end
5'b1_0111: begin
mpc_8241_rstb <=1'b0;
pmc_3386_1_rstb<=1'b1;
pmc_3386_2_rstb<=1'b0;
pmc_5381_rstb <=1'b0;
pmc_5382_rstb <=1'b0;
end
5'b1_1000: begin
mpc_8241_rstb <=1'b0;
pmc_3386_1_rstb<=1'b0;
pmc_3386_2_rstb<=1'b1;
pmc_5381_rstb <=1'b1;
pmc_5382_rstb <=1'b1;
end
5'b1_1001: begin
mpc_8241_rstb <=1'b0;
pmc_3386_1_rstb<=1'b0;
pmc_3386_2_rstb<=1'b1;
pmc_5381_rstb <=1'b1;
pmc_5382_rstb <=1'b0;
end
5'b1_1010: begin
mpc_8241_rstb <=1'b0;
pmc_3386_1_rstb<=1'b0;
pmc_3386_2_rstb<=1'b1;
pmc_5381_rstb <=1'b0;
pmc_5382_rstb <=1'b1;
end
5'b1_1011: begin
mpc_8241_rstb <=1'b0;
pmc_3386_1_rstb<=1'b0;
pmc_3386_2_rstb<=1'b1;
pmc_5381_rstb <=1'b0;
pmc_5382_rstb <=1'b0;
end
5'b1_1100: begin
mpc_8241_rstb <=1'b0;
pmc_3386_1_rstb<=1'b0;
pmc_3386_2_rstb<=1'b0;
pmc_5381_rstb <=1'b1;
pmc_5382_rstb <=1'b1;
end
5'b1_1101: begin
mpc_8241_rstb <=1'b0;
pmc_3386_1_rstb<=1'b0;
pmc_3386_2_rstb<=1'b0;
pmc_5381_rstb <=1'b1;
pmc_5382_rstb <=1'b0;
end
5'b1_1110: begin
mpc_8241_rstb <=1'b0;
pmc_3386_1_rstb<=1'b0;
pmc_3386_2_rstb<=1'b0;
pmc_5381_rstb <=1'b0;
pmc_5382_rstb <=1'b1;
end
5'b1_1111: begin
mpc_8241_rstb <=1'b0;
pmc_3386_1_rstb<=1'b0;
pmc_3386_2_rstb<=1'b0;
pmc_5381_rstb <=1'b0;
pmc_5382_rstb <=1'b0;
end
default: begin
mpc_8241_rstb <=1'b1;
pmc_3386_1_rstb<=1'b1;
pmc_3386_2_rstb<=1'b1;
pmc_5381_rstb <=1'b1;
pmc_5382_rstb <=1'b1;
end
endcase
end
else
begin
mpc_8241_rstb <=1'b1;
pmc_3386_1_rstb<=1'b1;
pmc_3386_2_rstb<=1'b1;
pmc_5381_rstb <=1'b1;
pmc_5382_rstb <=1'b1;
end
end
//write and read register signals
//xxx_csb_tmp
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
if(~h_reset_n)
begin
fpga_csb_tmp <=1'b1;
pmc_3386_1_csb_tmp <=1'b1;
pmc_3386_2_csb_tmp <=1'b1;
pmc_5381_csb_tmp <=1'b1;
pmc_5382_csb_tmp <=1'b1;
end
else if(~s_reset_n)
begin
fpga_csb_tmp <=1'b1;
pmc_3386_1_csb_tmp <=1'b1;
pmc_3386_2_csb_tmp <=1'b1;
pmc_5381_csb_tmp <=1'b1;
pmc_5382_csb_tmp <=1'b1;
end
else if(~mpc_csb)
begin
case(mpc_addr[15:13])
fpga_sel : begin
fpga_csb_tmp <=1'b0;
pmc_3386_1_csb_tmp <=1'b1;
pmc_3386_2_csb_tmp <=1'b1;
pmc_5381_csb_tmp <=1'b1;
pmc_5382_csb_tmp <=1'b1;
end
pmc3386_1_sel : begin
fpga_csb_tmp <=1'b1;
pmc_3386_1_csb_tmp <=1'b0;
pmc_3386_2_csb_tmp <=1'b1;
pmc_5381_csb_tmp <=1'b1;
pmc_5382_csb_tmp <=1'b1;
end
pmc3386_2_sel : begin
fpga_csb_tmp <=1'b1;
pmc_3386_1_csb_tmp <=1'b1;
pmc_3386_2_csb_tmp <=1'b0;
pmc_5381_csb_tmp <=1'b1;
pmc_5382_csb_tmp <=1'b1;
end
pmc5381_sel : begin
fpga_csb_tmp <=1'b1;
pmc_3386_1_csb_tmp <=1'b1;
pmc_3386_2_csb_tmp <=1'b1;
pmc_5381_csb_tmp <=1'b0;
pmc_5382_csb_tmp <=1'b1;
end
pmc5382_sel : begin
fpga_csb_tmp <=1'b1;
pmc_3386_1_csb_tmp <=1'b1;
pmc_3386_2_csb_tmp <=1'b1;
pmc_5381_csb_tmp <=1'b1;
pmc_5382_csb_tmp <=1'b0;
end
default : begin
fpga_csb_tmp <=1'b1;
pmc_3386_1_csb_tmp <=1'b1;
pmc_3386_2_csb_tmp <=1'b1;
pmc_5381_csb_tmp <=1'b1;
pmc_5382_csb_tmp <=1'b1;
end
endcase
end
else
begin
fpga_csb_tmp <=1'b1;
pmc_3386_1_csb_tmp <=1'b1;
pmc_3386_2_csb_tmp <=1'b1;
pmc_5381_csb_tmp <=1'b1;
pmc_5382_csb_tmp <=1'b1;
end
end
//csb_tmp_d,_2d
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
if(~h_reset_n)
begin
fpga_csb_tmp_d <=1'b1;
pmc_3386_1_csb_tmp_d <=1'b1;
pmc_3386_2_csb_tmp_d <=1'b1;
pmc_5381_csb_tmp_d <=1'b1;
pmc_5382_csb_tmp_d <=1'b1;
fpga_csb_tmp_2d <=1'b1;
pmc_3386_1_csb_tmp_2d <=1'b1;
pmc_3386_2_csb_tmp_2d <=1'b1;
pmc_5381_csb_tmp_2d <=1'b1;
pmc_5382_csb_tmp_2d <=1'b1;
end
else if(~s_reset_n)
begin
fpga_csb_tmp_d <=1'b1;
pmc_3386_1_csb_tmp_d <=1'b1;
pmc_3386_2_csb_tmp_d <=1'b1;
pmc_5381_csb_tmp_d <=1'b1;
pmc_5382_csb_tmp_d <=1'b1;
fpga_csb_tmp_2d <=1'b1;
pmc_3386_1_csb_tmp_2d <=1'b1;
pmc_3386_2_csb_tmp_2d <=1'b1;
pmc_5381_csb_tmp_2d <=1'b1;
pmc_5382_csb_tmp_2d <=1'b1;
end
else
begin
fpga_csb_tmp_d <=fpga_csb_tmp ;
pmc_3386_1_csb_tmp_d <=pmc_3386_1_csb_tmp;
pmc_3386_2_csb_tmp_d <=pmc_3386_2_csb_tmp;
pmc_5381_csb_tmp_d <=pmc_5381_csb_tmp ;
pmc_5382_csb_tmp_d <=pmc_5382_csb_tmp ;
fpga_csb_tmp_2d <=fpga_csb_tmp_d ;
pmc_3386_1_csb_tmp_2d <=pmc_3386_1_csb_tmp_d;
pmc_3386_2_csb_tmp_2d <=pmc_3386_2_csb_tmp_d;
pmc_5381_csb_tmp_2d <=pmc_5381_csb_tmp_d ;
pmc_5382_csb_tmp_2d <=pmc_5382_csb_tmp_d ;
end
end
//csb
//assign fpga_csb =fpga_csb_tmp || fpga_csb_tmp_2d;
//assign pmc_3386_1_csb =pmc_3386_1_csb_tmp || pmc_3386_1_csb_tmp_2d;
//assign pmc_3386_2_csb =pmc_3386_2_csb_tmp || pmc_3386_2_csb_tmp_2d;
//assign pmc_5381_csb =pmc_5381_csb_tmp || pmc_5381_csb_tmp_2d;
//assign pmc_5382_csb =pmc_5382_csb_tmp || pmc_5382_csb_tmp_2d;
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
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