shift_mult.v

来自「基于ＦＰＧＡ实现移位乘法功能」· Verilog 代码 · 共 33 行

module shift_mult(clk,Enable,a,p);
  parameter size=32;
  input clk;
  input Enable;
  input [size:1]a;
  output [2*size:1]p;
  reg [2*size:1]p,tempa,temp;
  reg [27:1]tempb;
  integer i;

  always@(posedge clk)
  if(!Enable)
    begin
      if(i==(size+1))
        begin
          p<=temp;
          i<=1;
          tempa<=a;
          tempb<=100000000;
          temp<=0;
        end
      else if(i<=size)
             begin
               if(tempb[1]) temp<=temp+tempa;
               tempa<=tempa<<1;
               tempb<=tempb>>1;
               i<=i+1;
             end
    end
  else p<=0;

endmodule