dds.tan.rpt

基于ＦＰＧＡ平台

; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+---------------------------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                                    ; From                                                                                                                                  ; To                                                                                                           ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 6.038 ns                                       ; Pword[1]                                                                                                                              ; REG10B:U5|Dout[9]                                                                                            ; --                           ; clk                          ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 8.858 ns                                       ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[6]                          ; Fout[6]                                                                                                      ; clk                          ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 3.056 ns                                       ; altera_internal_jtag~TDO                                                                                                              ; altera_reserved_tdo                                                                                          ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 1.979 ns                                       ; altera_internal_jtag~TMSUTAP                                                                                                          ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14]                                     ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 132.80 MHz ( period = 7.530 ns )               ; sld_hub:sld_hub_inst|jtag_debug_mode_usr1                                                                                             ; sld_hub:sld_hub_inst|hub_tdo                                                                                 ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clk'                          ; N/A   ; None          ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a3~porta_address_reg9 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[6] ; clk                          ; clk                          ; 0            ;
; Total number of failed paths                ;       ;               ;                                                ;                                                                                                                                       ;                                                                                                              ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C5T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;