dds.tan.rpt

来自「基于ＦＰＧＡ平台」· RPT 代码 · 共 206 行 · 第 1/5 页

+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk                          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                  ; To                                                                                                                                    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg0 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg1 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg2 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg3 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg4 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg5 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg6 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg7 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg8 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg9 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg0 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg1 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg2 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg3 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg4 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg5 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg6 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg7 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg8 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg9 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg0 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg1 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg2 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg3 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg4 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg5 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg6 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg7 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg8 ; Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;