clkdiv.vhd

vhdl语言描述分频器

LIBRARY IEEE; 

USE IEEE.STD_LOGIC_1164.ALL; 

USE IEEE.STD_LOGIC_ARITH.ALL; 

USE IEEE.STD_LOGIC_UNSIGNED.ALL; 

 

ENTITY clkdiv IS 

PORT(clk : IN STD_LOGIC; 

clk_div2 : OUT STD_LOGIC; 

clk_div4 : OUT STD_LOGIC; 

clk_div8 : OUT STD_LOGIC; 

clk_div16 : OUT STD_LOGIC); 

END clkdiv; 

  

ARCHITECTURE rtl OF clkdiv IS 

SIGNAL count : STD_LOGIC_VECTOR(3 DOWNTO 0); 

BEGIN 

PROCESS(clk) 

BEGIN 

IF (clk'event AND clk='1' ) THEN 

IF(count="1111") THEN 

count <= "0000"; 

ELSE 

count <= count +'1'; 

END IF ; 

END IF ; 

END PROCESS; 

clk_div2 <= count(0); 

clk_div4 <= count(1); 

clk_div8 <= count(2); 

clk_div16 <= count(3); 

END rtl;