clock_module.vhd

实现同一个时钟输入,可以实现多分频,在一个时钟的驱动下

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clock_module is
    Port (
				clk 	: in  STD_LOGIC;
				rst 	: in  STD_LOGIC;
				clk_K : out std_logic; -- for 扫描键盘
				clk_O : out std_logic
			);
end clock_module;

architecture Behavioral of clock_module is
signal counter : integer := 0;
signal counter1: integer := 0;
signal K       : std_logic:= '0';
signal O       : std_logic:= '0';
begin

	process(clk,rst)
		begin
			if rst = '1' then 
				counter <= 0;
				K <= '0';
				O <= '0';
			else 
				if clk'event and clk = '1' then
				if counter1 > 10000000 then -- clk frequency is 1000Hz 
					K <= not K;
					counter1 <= 0;
				else 
					counter1 <= counter1 + 1;
				end if;
				if counter > 2500000 then -- clk frequency is 10Hz
					O <= not O;
					counter <= 0;
				else 
					counter <= counter + 1;
				end if;
			end if;
		end if;
	end process;
	-------------------
	--output port
	-------------------
	clk_K <= K;
	clk_O <= O;
end Behavioral;