sintab_altera_v.sdo

在利用Verilog在FPGA平台上输出正弦波

    (DELAY
      (ABSOLUTE
        (PORT clk (1912:1912:1912) (1918:1918:1918))
        (PORT datain (108:108:108) (108:108:108))
        (PORT aclr (1928:1928:1928) (1921:1921:1921))
        (IOPATH (posedge clk) regout (304:304:304) (304:304:304))
        (IOPATH (posedge aclr) regout (267:267:267) (267:267:267))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (306:306:306))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE counter\[9\]\~108_I)
    (DELAY
      (ABSOLUTE
        (PORT datad (338:338:338) (441:441:441))
        (IOPATH datad combout (206:206:206) (206:206:206))
        (IOPATH cin combout (506:506:506) (506:506:506))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE counter\[9\]\~reg0_I)
    (DELAY
      (ABSOLUTE
        (PORT clk (1912:1912:1912) (1918:1918:1918))
        (PORT datain (108:108:108) (108:108:108))
        (PORT aclr (1928:1928:1928) (1921:1921:1921))
        (IOPATH (posedge clk) regout (304:304:304) (304:304:304))
        (IOPATH (posedge aclr) regout (267:267:267) (267:267:267))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (306:306:306))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (949:949:949) (1395:1395:1395))
        (PORT d[1] (949:949:949) (1395:1395:1395))
        (PORT d[2] (949:949:949) (1395:1395:1395))
        (PORT d[3] (949:949:949) (1395:1395:1395))
        (PORT clk (2007:2007:2007) (2021:2021:2021))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (267:267:267))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1064:1064:1064) (1510:1510:1510))
        (PORT d[1] (1067:1067:1067) (1510:1510:1510))
        (PORT d[2] (1066:1066:1066) (1512:1512:1512))
        (PORT d[3] (1362:1362:1362) (1897:1897:1897))
        (PORT d[4] (1351:1351:1351) (1889:1889:1889))
        (PORT d[5] (1412:1412:1412) (1915:1915:1915))
        (PORT d[6] (1329:1329:1329) (1874:1874:1874))
        (PORT d[7] (1337:1337:1337) (1883:1883:1883))
        (PORT d[8] (1364:1364:1364) (1902:1902:1902))
        (PORT d[9] (1343:1343:1343) (1886:1886:1886))
        (PORT clk (2008:2008:2008) (2022:2022:2022))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (267:267:267))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (384:384:384) (384:384:384))
        (PORT clk (2008:2008:2008) (2022:2022:2022))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (267:267:267))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a0.active_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2008:2008:2008) (2022:2022:2022))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2268:2268:2268) (2282:2282:2282))
        (IOPATH (posedge clk) pulse (0:0:0) (2161:2161:2161))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2268:2268:2268) (2282:2282:2282))
        (IOPATH (posedge clk) pulse (0:0:0) (2546:2546:2546))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2268:2268:2268) (2282:2282:2282))
        (IOPATH (posedge clk) pulse (0:0:0) (3641:3641:3641))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1988:1988:1988) (2002:2002:2002))
        (IOPATH (posedge clk) q (369:369:369) (369:369:369))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (267:267:267))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1232:1232:1232) (1773:1773:1773))
        (PORT d[1] (1239:1239:1239) (1781:1781:1781))
        (PORT d[2] (1239:1239:1239) (1781:1781:1781))
        (PORT d[3] (1232:1232:1232) (1773:1773:1773))
        (PORT clk (1986:1986:1986) (1999:1999:1999))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (267:267:267))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1048:1048:1048) (1498:1498:1498))
        (PORT d[1] (1091:1091:1091) (1530:1530:1530))
        (PORT d[2] (1056:1056:1056) (1505:1505:1505))
        (PORT d[3] (1338:1338:1338) (1880:1880:1880))
        (PORT d[4] (1346:1346:1346) (1885:1885:1885))
        (PORT d[5] (1352:1352:1352) (1892:1892:1892))
        (PORT d[6] (1689:1689:1689) (2313:2313:2313))
        (PORT d[7] (1672:1672:1672) (2298:2298:2298))
        (PORT d[8] (1344:1344:1344) (1886:1886:1886))
        (PORT d[9] (1684:1684:1684) (2307:2307:2307))
        (PORT clk (1987:1987:1987) (2000:2000:2000))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (267:267:267))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (384:384:384) (384:384:384))
        (PORT clk (1987:1987:1987) (2000:2000:2000))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (267:267:267))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a1.active_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1987:1987:1987) (2000:2000:2000))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2247:2247:2247) (2260:2260:2260))
        (IOPATH (posedge clk) pulse (0:0:0) (2161:2161:2161))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2247:2247:2247) (2260:2260:2260))
        (IOPATH (posedge clk) pulse (0:0:0) (2546:2546:2546))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2247:2247:2247) (2260:2260:2260))
        (IOPATH (posedge clk) pulse (0:0:0) (3641:3641:3641))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1967:1967:1967) (1980:1980:1980))
        (IOPATH (posedge clk) q (369:369:369) (369:369:369))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (267:267:267))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (895:895:895) (1358:1358:1358))
        (PORT d[1] (903:903:903) (1365:1365:1365))
        (PORT d[2] (903:903:903) (1365:1365:1365))
        (PORT d[3] (895:895:895) (1358:1358:1358))
        (PORT clk (2016:2016:2016) (2030:2030:2030))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (267:267:267))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1082:1082:1082) (1525:1525:1525))
        (PORT d[1] (1084:1084:1084) (1526:1526:1526))
        (PORT d[2] (1083:1083:1083) (1527:1527:1527))
        (PORT d[3] (1376:1376:1376) (1913:1913:1913))
        (PORT d[4] (1379:1379:1379) (1916:1916:1916))
        (PORT d[5] (1436:1436:1436) (1931:1931:1931))
        (PORT d[6] (1334:1334:1334) (1879:1879:1879))
        (PORT d[7] (1670:1670:1670) (2294:2294:2294))
        (PORT d[8] (1380:1380:1380) (1916:1916:1916))
        (PORT d[9] (1353:1353:1353) (1896:1896:1896))
        (PORT clk (2017:2017:2017) (2031:2031:2031))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (267:267:267))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (384:384:384) (384:384:384))
        (PORT clk (2017:2017:2017) (2031:2031:2031))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (267:267:267))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a2.active_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2017:2017:2017) (2031:2031:2031))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2277:2277:2277) (2291:2291:2291))
        (IOPATH (posedge clk) pulse (0:0:0) (2161:2161:2161))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2277:2277:2277) (2291:2291:2291))
        (IOPATH (posedge clk) pulse (0:0:0) (2546:2546:2546))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2277:2277:2277) (2291:2291:2291))
        (IOPATH (posedge clk) pulse (0:0:0) (3641:3641:3641))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE sintab1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1997:1997:1997) (2011:2011:2011))
        (IOPATH (posedge clk) q (369:369:369) (369:369:369))