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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--D1_q_a[0] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[0] at M4K_X43_Y35
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[0]_PORT_A_data_in = BUS(~GND, ~GND, ~GND, ~GND);
D1_q_a[0]_PORT_A_data_in_reg = DFFE(D1_q_a[0]_PORT_A_data_in, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_write_enable = GND;
D1_q_a[0]_PORT_A_write_enable_reg = DFFE(D1_q_a[0]_PORT_A_write_enable, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = GLOBAL(A1L60);
D1_q_a[0]_PORT_A_data_out = MEMORY(D1_q_a[0]_PORT_A_data_in_reg, , D1_q_a[0]_PORT_A_address_reg, , D1_q_a[0]_PORT_A_write_enable_reg, , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[0]_PORT_A_data_out_reg = DFFE(D1_q_a[0]_PORT_A_data_out, D1_q_a[0]_clock_0, , , );
D1_q_a[0] = D1_q_a[0]_PORT_A_data_out_reg[0];

--D1_q_a[9] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[9] at M4K_X43_Y35
D1_q_a[0]_PORT_A_data_in = BUS(~GND, ~GND, ~GND, ~GND);
D1_q_a[0]_PORT_A_data_in_reg = DFFE(D1_q_a[0]_PORT_A_data_in, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_write_enable = GND;
D1_q_a[0]_PORT_A_write_enable_reg = DFFE(D1_q_a[0]_PORT_A_write_enable, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = GLOBAL(A1L60);
D1_q_a[0]_PORT_A_data_out = MEMORY(D1_q_a[0]_PORT_A_data_in_reg, , D1_q_a[0]_PORT_A_address_reg, , D1_q_a[0]_PORT_A_write_enable_reg, , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[0]_PORT_A_data_out_reg = DFFE(D1_q_a[0]_PORT_A_data_out, D1_q_a[0]_clock_0, , , );
D1_q_a[9] = D1_q_a[0]_PORT_A_data_out_reg[3];

--D1_q_a[8] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[8] at M4K_X43_Y35
D1_q_a[0]_PORT_A_data_in = BUS(~GND, ~GND, ~GND, ~GND);
D1_q_a[0]_PORT_A_data_in_reg = DFFE(D1_q_a[0]_PORT_A_data_in, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_write_enable = GND;
D1_q_a[0]_PORT_A_write_enable_reg = DFFE(D1_q_a[0]_PORT_A_write_enable, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = GLOBAL(A1L60);
D1_q_a[0]_PORT_A_data_out = MEMORY(D1_q_a[0]_PORT_A_data_in_reg, , D1_q_a[0]_PORT_A_address_reg, , D1_q_a[0]_PORT_A_write_enable_reg, , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[0]_PORT_A_data_out_reg = DFFE(D1_q_a[0]_PORT_A_data_out, D1_q_a[0]_clock_0, , , );
D1_q_a[8] = D1_q_a[0]_PORT_A_data_out_reg[2];

--D1_q_a[7] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[7] at M4K_X43_Y35
D1_q_a[0]_PORT_A_data_in = BUS(~GND, ~GND, ~GND, ~GND);
D1_q_a[0]_PORT_A_data_in_reg = DFFE(D1_q_a[0]_PORT_A_data_in, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_write_enable = GND;
D1_q_a[0]_PORT_A_write_enable_reg = DFFE(D1_q_a[0]_PORT_A_write_enable, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = GLOBAL(A1L60);
D1_q_a[0]_PORT_A_data_out = MEMORY(D1_q_a[0]_PORT_A_data_in_reg, , D1_q_a[0]_PORT_A_address_reg, , D1_q_a[0]_PORT_A_write_enable_reg, , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[0]_PORT_A_data_out_reg = DFFE(D1_q_a[0]_PORT_A_data_out, D1_q_a[0]_clock_0, , , );
D1_q_a[7] = D1_q_a[0]_PORT_A_data_out_reg[1];


--D1_q_a[1] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[1] at M4K_X43_Y33
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[1]_PORT_A_data_in = BUS(~GND, ~GND, ~GND, ~GND);
D1_q_a[1]_PORT_A_data_in_reg = DFFE(D1_q_a[1]_PORT_A_data_in, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[1]_PORT_A_address_reg = DFFE(D1_q_a[1]_PORT_A_address, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_PORT_A_write_enable = GND;
D1_q_a[1]_PORT_A_write_enable_reg = DFFE(D1_q_a[1]_PORT_A_write_enable, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_clock_0 = GLOBAL(A1L60);
D1_q_a[1]_PORT_A_data_out = MEMORY(D1_q_a[1]_PORT_A_data_in_reg, , D1_q_a[1]_PORT_A_address_reg, , D1_q_a[1]_PORT_A_write_enable_reg, , , , D1_q_a[1]_clock_0, , , , , );
D1_q_a[1]_PORT_A_data_out_reg = DFFE(D1_q_a[1]_PORT_A_data_out, D1_q_a[1]_clock_0, , , );
D1_q_a[1] = D1_q_a[1]_PORT_A_data_out_reg[0];

--D1_q_a[13] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[13] at M4K_X43_Y33
D1_q_a[1]_PORT_A_data_in = BUS(~GND, ~GND, ~GND, ~GND);
D1_q_a[1]_PORT_A_data_in_reg = DFFE(D1_q_a[1]_PORT_A_data_in, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[1]_PORT_A_address_reg = DFFE(D1_q_a[1]_PORT_A_address, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_PORT_A_write_enable = GND;
D1_q_a[1]_PORT_A_write_enable_reg = DFFE(D1_q_a[1]_PORT_A_write_enable, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_clock_0 = GLOBAL(A1L60);
D1_q_a[1]_PORT_A_data_out = MEMORY(D1_q_a[1]_PORT_A_data_in_reg, , D1_q_a[1]_PORT_A_address_reg, , D1_q_a[1]_PORT_A_write_enable_reg, , , , D1_q_a[1]_clock_0, , , , , );
D1_q_a[1]_PORT_A_data_out_reg = DFFE(D1_q_a[1]_PORT_A_data_out, D1_q_a[1]_clock_0, , , );
D1_q_a[13] = D1_q_a[1]_PORT_A_data_out_reg[3];

--D1_q_a[10] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[10] at M4K_X43_Y33
D1_q_a[1]_PORT_A_data_in = BUS(~GND, ~GND, ~GND, ~GND);
D1_q_a[1]_PORT_A_data_in_reg = DFFE(D1_q_a[1]_PORT_A_data_in, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[1]_PORT_A_address_reg = DFFE(D1_q_a[1]_PORT_A_address, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_PORT_A_write_enable = GND;
D1_q_a[1]_PORT_A_write_enable_reg = DFFE(D1_q_a[1]_PORT_A_write_enable, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_clock_0 = GLOBAL(A1L60);
D1_q_a[1]_PORT_A_data_out = MEMORY(D1_q_a[1]_PORT_A_data_in_reg, , D1_q_a[1]_PORT_A_address_reg, , D1_q_a[1]_PORT_A_write_enable_reg, , , , D1_q_a[1]_clock_0, , , , , );
D1_q_a[1]_PORT_A_data_out_reg = DFFE(D1_q_a[1]_PORT_A_data_out, D1_q_a[1]_clock_0, , , );
D1_q_a[10] = D1_q_a[1]_PORT_A_data_out_reg[2];

--D1_q_a[5] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[5] at M4K_X43_Y33
D1_q_a[1]_PORT_A_data_in = BUS(~GND, ~GND, ~GND, ~GND);
D1_q_a[1]_PORT_A_data_in_reg = DFFE(D1_q_a[1]_PORT_A_data_in, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[1]_PORT_A_address_reg = DFFE(D1_q_a[1]_PORT_A_address, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_PORT_A_write_enable = GND;
D1_q_a[1]_PORT_A_write_enable_reg = DFFE(D1_q_a[1]_PORT_A_write_enable, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_clock_0 = GLOBAL(A1L60);
D1_q_a[1]_PORT_A_data_out = MEMORY(D1_q_a[1]_PORT_A_data_in_reg, , D1_q_a[1]_PORT_A_address_reg, , D1_q_a[1]_PORT_A_write_enable_reg, , , , D1_q_a[1]_clock_0, , , , , );
D1_q_a[1]_PORT_A_data_out_reg = DFFE(D1_q_a[1]_PORT_A_data_out, D1_q_a[1]_clock_0, , , );
D1_q_a[5] = D1_q_a[1]_PORT_A_data_out_reg[1];


--D1_q_a[2] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[2] at M4K_X43_Y36
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[2]_PORT_A_data_in = BUS(~GND, ~GND, ~GND, ~GND);
D1_q_a[2]_PORT_A_data_in_reg = DFFE(D1_q_a[2]_PORT_A_data_in, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[2]_PORT_A_address_reg = DFFE(D1_q_a[2]_PORT_A_address, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_PORT_A_write_enable = GND;
D1_q_a[2]_PORT_A_write_enable_reg = DFFE(D1_q_a[2]_PORT_A_write_enable, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_clock_0 = GLOBAL(A1L60);
D1_q_a[2]_PORT_A_data_out = MEMORY(D1_q_a[2]_PORT_A_data_in_reg, , D1_q_a[2]_PORT_A_address_reg, , D1_q_a[2]_PORT_A_write_enable_reg, , , , D1_q_a[2]_clock_0, , , , , );
D1_q_a[2]_PORT_A_data_out_reg = DFFE(D1_q_a[2]_PORT_A_data_out, D1_q_a[2]_clock_0, , , );
D1_q_a[2] = D1_q_a[2]_PORT_A_data_out_reg[0];

--D1_q_a[12] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[12] at M4K_X43_Y36
D1_q_a[2]_PORT_A_data_in = BUS(~GND, ~GND, ~GND, ~GND);
D1_q_a[2]_PORT_A_data_in_reg = DFFE(D1_q_a[2]_PORT_A_data_in, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[2]_PORT_A_address_reg = DFFE(D1_q_a[2]_PORT_A_address, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_PORT_A_write_enable = GND;
D1_q_a[2]_PORT_A_write_enable_reg = DFFE(D1_q_a[2]_PORT_A_write_enable, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_clock_0 = GLOBAL(A1L60);
D1_q_a[2]_PORT_A_data_out = MEMORY(D1_q_a[2]_PORT_A_data_in_reg, , D1_q_a[2]_PORT_A_address_reg, , D1_q_a[2]_PORT_A_write_enable_reg, , , , D1_q_a[2]_clock_0, , , , , );
D1_q_a[2]_PORT_A_data_out_reg = DFFE(D1_q_a[2]_PORT_A_data_out, D1_q_a[2]_clock_0, , , );
D1_q_a[12] = D1_q_a[2]_PORT_A_data_out_reg[3];

--D1_q_a[6] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[6] at M4K_X43_Y36
D1_q_a[2]_PORT_A_data_in = BUS(~GND, ~GND, ~GND, ~GND);
D1_q_a[2]_PORT_A_data_in_reg = DFFE(D1_q_a[2]_PORT_A_data_in, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[2]_PORT_A_address_reg = DFFE(D1_q_a[2]_PORT_A_address, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_PORT_A_write_enable = GND;
D1_q_a[2]_PORT_A_write_enable_reg = DFFE(D1_q_a[2]_PORT_A_write_enable, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_clock_0 = GLOBAL(A1L60);
D1_q_a[2]_PORT_A_data_out = MEMORY(D1_q_a[2]_PORT_A_data_in_reg, , D1_q_a[2]_PORT_A_address_reg, , D1_q_a[2]_PORT_A_write_enable_reg, , , , D1_q_a[2]_clock_0, , , , , );
D1_q_a[2]_PORT_A_data_out_reg = DFFE(D1_q_a[2]_PORT_A_data_out, D1_q_a[2]_clock_0, , , );
D1_q_a[6] = D1_q_a[2]_PORT_A_data_out_reg[2];

--D1_q_a[3] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[3] at M4K_X43_Y36
D1_q_a[2]_PORT_A_data_in = BUS(~GND, ~GND, ~GND, ~GND);
D1_q_a[2]_PORT_A_data_in_reg = DFFE(D1_q_a[2]_PORT_A_data_in, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[2]_PORT_A_address_reg = DFFE(D1_q_a[2]_PORT_A_address, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_PORT_A_write_enable = GND;
D1_q_a[2]_PORT_A_write_enable_reg = DFFE(D1_q_a[2]_PORT_A_write_enable, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_clock_0 = GLOBAL(A1L60);
D1_q_a[2]_PORT_A_data_out = MEMORY(D1_q_a[2]_PORT_A_data_in_reg, , D1_q_a[2]_PORT_A_address_reg, , D1_q_a[2]_PORT_A_write_enable_reg, , , , D1_q_a[2]_clock_0, , , , , );
D1_q_a[2]_PORT_A_data_out_reg = DFFE(D1_q_a[2]_PORT_A_data_out, D1_q_a[2]_clock_0, , , );
D1_q_a[3] = D1_q_a[2]_PORT_A_data_out_reg[1];


--D1_q_a[4] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[4] at M4K_X43_Y34
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 2
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[4]_PORT_A_data_in = BUS(~GND, ~GND);
D1_q_a[4]_PORT_A_data_in_reg = DFFE(D1_q_a[4]_PORT_A_data_in, D1_q_a[4]_clock_0, , , );
D1_q_a[4]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[4]_PORT_A_address_reg = DFFE(D1_q_a[4]_PORT_A_address, D1_q_a[4]_clock_0, , , );
D1_q_a[4]_PORT_A_write_enable = GND;
D1_q_a[4]_PORT_A_write_enable_reg = DFFE(D1_q_a[4]_PORT_A_write_enable, D1_q_a[4]_clock_0, , , );
D1_q_a[4]_clock_0 = GLOBAL(A1L60);
D1_q_a[4]_PORT_A_data_out = MEMORY(D1_q_a[4]_PORT_A_data_in_reg, , D1_q_a[4]_PORT_A_address_reg, , D1_q_a[4]_PORT_A_write_enable_reg, , , , D1_q_a[4]_clock_0, , , , , );
D1_q_a[4]_PORT_A_data_out_reg = DFFE(D1_q_a[4]_PORT_A_data_out, D1_q_a[4]_clock_0, , , );
D1_q_a[4] = D1_q_a[4]_PORT_A_data_out_reg[0];

--D1_q_a[11] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11] at M4K_X43_Y34
D1_q_a[4]_PORT_A_data_in = BUS(~GND, ~GND);
D1_q_a[4]_PORT_A_data_in_reg = DFFE(D1_q_a[4]_PORT_A_data_in, D1_q_a[4]_clock_0, , , );
D1_q_a[4]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[4]_PORT_A_address_reg = DFFE(D1_q_a[4]_PORT_A_address, D1_q_a[4]_clock_0, , , );
D1_q_a[4]_PORT_A_write_enable = GND;
D1_q_a[4]_PORT_A_write_enable_reg = DFFE(D1_q_a[4]_PORT_A_write_enable, D1_q_a[4]_clock_0, , , );
D1_q_a[4]_clock_0 = GLOBAL(A1L60);
D1_q_a[4]_PORT_A_data_out = MEMORY(D1_q_a[4]_PORT_A_data_in_reg, , D1_q_a[4]_PORT_A_address_reg, , D1_q_a[4]_PORT_A_write_enable_reg, , , , D1_q_a[4]_clock_0, , , , , );
D1_q_a[4]_PORT_A_data_out_reg = DFFE(D1_q_a[4]_PORT_A_data_out, D1_q_a[4]_clock_0, , , );
D1_q_a[11] = D1_q_a[4]_PORT_A_data_out_reg[1];


--A1L5Q is counter[0]~reg0 at LCFF_X42_Y34_N13
A1L5Q = DFFEAS(A1L3, GLOBAL(A1L60), GLOBAL(A1L43),  ,  ,  ,  ,  ,  );


--A1L9Q is counter[1]~reg0 at LCFF_X42_Y34_N15
A1L9Q = DFFEAS(A1L7, GLOBAL(A1L60), GLOBAL(A1L43),  ,  ,  ,  ,  ,  );


--A1L13Q is counter[2]~reg0 at LCFF_X42_Y34_N17
A1L13Q = DFFEAS(A1L11, GLOBAL(A1L60), GLOBAL(A1L43),  ,  ,  ,  ,  ,  );


--A1L17Q is counter[3]~reg0 at LCFF_X42_Y34_N19
A1L17Q = DFFEAS(A1L15, GLOBAL(A1L60), GLOBAL(A1L43),  ,  ,  ,  ,  ,  );


--A1L21Q is counter[4]~reg0 at LCFF_X42_Y34_N21
A1L21Q = DFFEAS(A1L19, GLOBAL(A1L60), GLOBAL(A1L43),  ,  ,  ,  ,  ,  );


--A1L25Q is counter[5]~reg0 at LCFF_X42_Y34_N23
A1L25Q = DFFEAS(A1L23, GLOBAL(A1L60), GLOBAL(A1L43),  ,  ,  ,  ,  ,  );


--A1L29Q is counter[6]~reg0 at LCFF_X42_Y34_N25
A1L29Q = DFFEAS(A1L27, GLOBAL(A1L60), GLOBAL(A1L43),  ,  ,  ,  ,  ,  );


--A1L33Q is counter[7]~reg0 at LCFF_X42_Y34_N27
A1L33Q = DFFEAS(A1L31, GLOBAL(A1L60), GLOBAL(A1L43),  ,  ,  ,  ,  ,  );


--A1L37Q is counter[8]~reg0 at LCFF_X42_Y34_N29
A1L37Q = DFFEAS(A1L35, GLOBAL(A1L60), GLOBAL(A1L43),  ,  ,  ,  ,  ,  );


--A1L41Q is counter[9]~reg0 at LCFF_X42_Y34_N31
A1L41Q = DFFEAS(A1L39, GLOBAL(A1L60), GLOBAL(A1L43),  ,  ,  ,  ,  ,  );
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