sintab_altera.map.eqn

在利用Verilog在FPGA平台上输出正弦波

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--D1_q_a[0] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[0]
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[0]_PORT_A_data_in = ~GND;
D1_q_a[0]_PORT_A_data_in_reg = DFFE(D1_q_a[0]_PORT_A_data_in, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_B_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[0]_PORT_B_address_reg = DFFE(D1_q_a[0]_PORT_B_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_write_enable = GND;
D1_q_a[0]_PORT_A_write_enable_reg = DFFE(D1_q_a[0]_PORT_A_write_enable, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = sys_clk;
D1_q_a[0]_PORT_A_data_out = MEMORY(D1_q_a[0]_PORT_A_data_in_reg, , D1_q_a[0]_PORT_A_address_reg, D1_q_a[0]_PORT_B_address_reg, D1_q_a[0]_PORT_A_write_enable_reg, , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[0]_PORT_A_data_out_reg = DFFE(D1_q_a[0]_PORT_A_data_out, D1_q_a[0]_clock_0, , , );
D1_q_a[0] = D1_q_a[0]_PORT_A_data_out_reg[0];


--D1_q_a[1] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[1]
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[1]_PORT_A_data_in = ~GND;
D1_q_a[1]_PORT_A_data_in_reg = DFFE(D1_q_a[1]_PORT_A_data_in, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[1]_PORT_A_address_reg = DFFE(D1_q_a[1]_PORT_A_address, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_PORT_B_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[1]_PORT_B_address_reg = DFFE(D1_q_a[1]_PORT_B_address, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_PORT_A_write_enable = GND;
D1_q_a[1]_PORT_A_write_enable_reg = DFFE(D1_q_a[1]_PORT_A_write_enable, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_clock_0 = sys_clk;
D1_q_a[1]_PORT_A_data_out = MEMORY(D1_q_a[1]_PORT_A_data_in_reg, , D1_q_a[1]_PORT_A_address_reg, D1_q_a[1]_PORT_B_address_reg, D1_q_a[1]_PORT_A_write_enable_reg, , , , D1_q_a[1]_clock_0, , , , , );
D1_q_a[1]_PORT_A_data_out_reg = DFFE(D1_q_a[1]_PORT_A_data_out, D1_q_a[1]_clock_0, , , );
D1_q_a[1] = D1_q_a[1]_PORT_A_data_out_reg[0];


--D1_q_a[2] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[2]
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[2]_PORT_A_data_in = ~GND;
D1_q_a[2]_PORT_A_data_in_reg = DFFE(D1_q_a[2]_PORT_A_data_in, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[2]_PORT_A_address_reg = DFFE(D1_q_a[2]_PORT_A_address, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_PORT_B_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[2]_PORT_B_address_reg = DFFE(D1_q_a[2]_PORT_B_address, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_PORT_A_write_enable = GND;
D1_q_a[2]_PORT_A_write_enable_reg = DFFE(D1_q_a[2]_PORT_A_write_enable, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_clock_0 = sys_clk;
D1_q_a[2]_PORT_A_data_out = MEMORY(D1_q_a[2]_PORT_A_data_in_reg, , D1_q_a[2]_PORT_A_address_reg, D1_q_a[2]_PORT_B_address_reg, D1_q_a[2]_PORT_A_write_enable_reg, , , , D1_q_a[2]_clock_0, , , , , );
D1_q_a[2]_PORT_A_data_out_reg = DFFE(D1_q_a[2]_PORT_A_data_out, D1_q_a[2]_clock_0, , , );
D1_q_a[2] = D1_q_a[2]_PORT_A_data_out_reg[0];


--D1_q_a[3] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[3]
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[3]_PORT_A_data_in = ~GND;
D1_q_a[3]_PORT_A_data_in_reg = DFFE(D1_q_a[3]_PORT_A_data_in, D1_q_a[3]_clock_0, , , );
D1_q_a[3]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[3]_PORT_A_address_reg = DFFE(D1_q_a[3]_PORT_A_address, D1_q_a[3]_clock_0, , , );
D1_q_a[3]_PORT_B_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[3]_PORT_B_address_reg = DFFE(D1_q_a[3]_PORT_B_address, D1_q_a[3]_clock_0, , , );
D1_q_a[3]_PORT_A_write_enable = GND;
D1_q_a[3]_PORT_A_write_enable_reg = DFFE(D1_q_a[3]_PORT_A_write_enable, D1_q_a[3]_clock_0, , , );
D1_q_a[3]_clock_0 = sys_clk;
D1_q_a[3]_PORT_A_data_out = MEMORY(D1_q_a[3]_PORT_A_data_in_reg, , D1_q_a[3]_PORT_A_address_reg, D1_q_a[3]_PORT_B_address_reg, D1_q_a[3]_PORT_A_write_enable_reg, , , , D1_q_a[3]_clock_0, , , , , );
D1_q_a[3]_PORT_A_data_out_reg = DFFE(D1_q_a[3]_PORT_A_data_out, D1_q_a[3]_clock_0, , , );
D1_q_a[3] = D1_q_a[3]_PORT_A_data_out_reg[0];


--D1_q_a[4] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[4]
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[4]_PORT_A_data_in = ~GND;
D1_q_a[4]_PORT_A_data_in_reg = DFFE(D1_q_a[4]_PORT_A_data_in, D1_q_a[4]_clock_0, , , );
D1_q_a[4]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[4]_PORT_A_address_reg = DFFE(D1_q_a[4]_PORT_A_address, D1_q_a[4]_clock_0, , , );
D1_q_a[4]_PORT_B_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[4]_PORT_B_address_reg = DFFE(D1_q_a[4]_PORT_B_address, D1_q_a[4]_clock_0, , , );
D1_q_a[4]_PORT_A_write_enable = GND;
D1_q_a[4]_PORT_A_write_enable_reg = DFFE(D1_q_a[4]_PORT_A_write_enable, D1_q_a[4]_clock_0, , , );
D1_q_a[4]_clock_0 = sys_clk;
D1_q_a[4]_PORT_A_data_out = MEMORY(D1_q_a[4]_PORT_A_data_in_reg, , D1_q_a[4]_PORT_A_address_reg, D1_q_a[4]_PORT_B_address_reg, D1_q_a[4]_PORT_A_write_enable_reg, , , , D1_q_a[4]_clock_0, , , , , );
D1_q_a[4]_PORT_A_data_out_reg = DFFE(D1_q_a[4]_PORT_A_data_out, D1_q_a[4]_clock_0, , , );
D1_q_a[4] = D1_q_a[4]_PORT_A_data_out_reg[0];


--D1_q_a[5] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[5]
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[5]_PORT_A_data_in = ~GND;
D1_q_a[5]_PORT_A_data_in_reg = DFFE(D1_q_a[5]_PORT_A_data_in, D1_q_a[5]_clock_0, , , );
D1_q_a[5]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[5]_PORT_A_address_reg = DFFE(D1_q_a[5]_PORT_A_address, D1_q_a[5]_clock_0, , , );
D1_q_a[5]_PORT_B_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[5]_PORT_B_address_reg = DFFE(D1_q_a[5]_PORT_B_address, D1_q_a[5]_clock_0, , , );
D1_q_a[5]_PORT_A_write_enable = GND;
D1_q_a[5]_PORT_A_write_enable_reg = DFFE(D1_q_a[5]_PORT_A_write_enable, D1_q_a[5]_clock_0, , , );
D1_q_a[5]_clock_0 = sys_clk;
D1_q_a[5]_PORT_A_data_out = MEMORY(D1_q_a[5]_PORT_A_data_in_reg, , D1_q_a[5]_PORT_A_address_reg, D1_q_a[5]_PORT_B_address_reg, D1_q_a[5]_PORT_A_write_enable_reg, , , , D1_q_a[5]_clock_0, , , , , );
D1_q_a[5]_PORT_A_data_out_reg = DFFE(D1_q_a[5]_PORT_A_data_out, D1_q_a[5]_clock_0, , , );
D1_q_a[5] = D1_q_a[5]_PORT_A_data_out_reg[0];


--D1_q_a[6] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[6]
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[6]_PORT_A_data_in = ~GND;
D1_q_a[6]_PORT_A_data_in_reg = DFFE(D1_q_a[6]_PORT_A_data_in, D1_q_a[6]_clock_0, , , );
D1_q_a[6]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[6]_PORT_A_address_reg = DFFE(D1_q_a[6]_PORT_A_address, D1_q_a[6]_clock_0, , , );
D1_q_a[6]_PORT_B_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[6]_PORT_B_address_reg = DFFE(D1_q_a[6]_PORT_B_address, D1_q_a[6]_clock_0, , , );
D1_q_a[6]_PORT_A_write_enable = GND;
D1_q_a[6]_PORT_A_write_enable_reg = DFFE(D1_q_a[6]_PORT_A_write_enable, D1_q_a[6]_clock_0, , , );
D1_q_a[6]_clock_0 = sys_clk;
D1_q_a[6]_PORT_A_data_out = MEMORY(D1_q_a[6]_PORT_A_data_in_reg, , D1_q_a[6]_PORT_A_address_reg, D1_q_a[6]_PORT_B_address_reg, D1_q_a[6]_PORT_A_write_enable_reg, , , , D1_q_a[6]_clock_0, , , , , );
D1_q_a[6]_PORT_A_data_out_reg = DFFE(D1_q_a[6]_PORT_A_data_out, D1_q_a[6]_clock_0, , , );
D1_q_a[6] = D1_q_a[6]_PORT_A_data_out_reg[0];


--D1_q_a[7] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[7]
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[7]_PORT_A_data_in = ~GND;
D1_q_a[7]_PORT_A_data_in_reg = DFFE(D1_q_a[7]_PORT_A_data_in, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[7]_PORT_A_address_reg = DFFE(D1_q_a[7]_PORT_A_address, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_PORT_B_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[7]_PORT_B_address_reg = DFFE(D1_q_a[7]_PORT_B_address, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_PORT_A_write_enable = GND;
D1_q_a[7]_PORT_A_write_enable_reg = DFFE(D1_q_a[7]_PORT_A_write_enable, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_clock_0 = sys_clk;
D1_q_a[7]_PORT_A_data_out = MEMORY(D1_q_a[7]_PORT_A_data_in_reg, , D1_q_a[7]_PORT_A_address_reg, D1_q_a[7]_PORT_B_address_reg, D1_q_a[7]_PORT_A_write_enable_reg, , , , D1_q_a[7]_clock_0, , , , , );
D1_q_a[7]_PORT_A_data_out_reg = DFFE(D1_q_a[7]_PORT_A_data_out, D1_q_a[7]_clock_0, , , );
D1_q_a[7] = D1_q_a[7]_PORT_A_data_out_reg[0];


--D1_q_a[8] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[8]
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[8]_PORT_A_data_in = ~GND;
D1_q_a[8]_PORT_A_data_in_reg = DFFE(D1_q_a[8]_PORT_A_data_in, D1_q_a[8]_clock_0, , , );
D1_q_a[8]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[8]_PORT_A_address_reg = DFFE(D1_q_a[8]_PORT_A_address, D1_q_a[8]_clock_0, , , );
D1_q_a[8]_PORT_B_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[8]_PORT_B_address_reg = DFFE(D1_q_a[8]_PORT_B_address, D1_q_a[8]_clock_0, , , );
D1_q_a[8]_PORT_A_write_enable = GND;
D1_q_a[8]_PORT_A_write_enable_reg = DFFE(D1_q_a[8]_PORT_A_write_enable, D1_q_a[8]_clock_0, , , );
D1_q_a[8]_clock_0 = sys_clk;
D1_q_a[8]_PORT_A_data_out = MEMORY(D1_q_a[8]_PORT_A_data_in_reg, , D1_q_a[8]_PORT_A_address_reg, D1_q_a[8]_PORT_B_address_reg, D1_q_a[8]_PORT_A_write_enable_reg, , , , D1_q_a[8]_clock_0, , , , , );
D1_q_a[8]_PORT_A_data_out_reg = DFFE(D1_q_a[8]_PORT_A_data_out, D1_q_a[8]_clock_0, , , );
D1_q_a[8] = D1_q_a[8]_PORT_A_data_out_reg[0];


--D1_q_a[9] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[9]
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[9]_PORT_A_data_in = ~GND;
D1_q_a[9]_PORT_A_data_in_reg = DFFE(D1_q_a[9]_PORT_A_data_in, D1_q_a[9]_clock_0, , , );
D1_q_a[9]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[9]_PORT_A_address_reg = DFFE(D1_q_a[9]_PORT_A_address, D1_q_a[9]_clock_0, , , );
D1_q_a[9]_PORT_B_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[9]_PORT_B_address_reg = DFFE(D1_q_a[9]_PORT_B_address, D1_q_a[9]_clock_0, , , );
D1_q_a[9]_PORT_A_write_enable = GND;
D1_q_a[9]_PORT_A_write_enable_reg = DFFE(D1_q_a[9]_PORT_A_write_enable, D1_q_a[9]_clock_0, , , );
D1_q_a[9]_clock_0 = sys_clk;
D1_q_a[9]_PORT_A_data_out = MEMORY(D1_q_a[9]_PORT_A_data_in_reg, , D1_q_a[9]_PORT_A_address_reg, D1_q_a[9]_PORT_B_address_reg, D1_q_a[9]_PORT_A_write_enable_reg, , , , D1_q_a[9]_clock_0, , , , , );
D1_q_a[9]_PORT_A_data_out_reg = DFFE(D1_q_a[9]_PORT_A_data_out, D1_q_a[9]_clock_0, , , );
D1_q_a[9] = D1_q_a[9]_PORT_A_data_out_reg[0];


--D1_q_a[10] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[10]
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[10]_PORT_A_data_in = ~GND;
D1_q_a[10]_PORT_A_data_in_reg = DFFE(D1_q_a[10]_PORT_A_data_in, D1_q_a[10]_clock_0, , , );
D1_q_a[10]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[10]_PORT_A_address_reg = DFFE(D1_q_a[10]_PORT_A_address, D1_q_a[10]_clock_0, , , );
D1_q_a[10]_PORT_B_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[10]_PORT_B_address_reg = DFFE(D1_q_a[10]_PORT_B_address, D1_q_a[10]_clock_0, , , );
D1_q_a[10]_PORT_A_write_enable = GND;
D1_q_a[10]_PORT_A_write_enable_reg = DFFE(D1_q_a[10]_PORT_A_write_enable, D1_q_a[10]_clock_0, , , );
D1_q_a[10]_clock_0 = sys_clk;
D1_q_a[10]_PORT_A_data_out = MEMORY(D1_q_a[10]_PORT_A_data_in_reg, , D1_q_a[10]_PORT_A_address_reg, D1_q_a[10]_PORT_B_address_reg, D1_q_a[10]_PORT_A_write_enable_reg, , , , D1_q_a[10]_clock_0, , , , , );
D1_q_a[10]_PORT_A_data_out_reg = DFFE(D1_q_a[10]_PORT_A_data_out, D1_q_a[10]_clock_0, , , );
D1_q_a[10] = D1_q_a[10]_PORT_A_data_out_reg[0];


--D1_q_a[11] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11]
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[11]_PORT_A_data_in = ~GND;
D1_q_a[11]_PORT_A_data_in_reg = DFFE(D1_q_a[11]_PORT_A_data_in, D1_q_a[11]_clock_0, , , );
D1_q_a[11]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[11]_PORT_A_address_reg = DFFE(D1_q_a[11]_PORT_A_address, D1_q_a[11]_clock_0, , , );
D1_q_a[11]_PORT_B_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[11]_PORT_B_address_reg = DFFE(D1_q_a[11]_PORT_B_address, D1_q_a[11]_clock_0, , , );
D1_q_a[11]_PORT_A_write_enable = GND;
D1_q_a[11]_PORT_A_write_enable_reg = DFFE(D1_q_a[11]_PORT_A_write_enable, D1_q_a[11]_clock_0, , , );
D1_q_a[11]_clock_0 = sys_clk;
D1_q_a[11]_PORT_A_data_out = MEMORY(D1_q_a[11]_PORT_A_data_in_reg, , D1_q_a[11]_PORT_A_address_reg, D1_q_a[11]_PORT_B_address_reg, D1_q_a[11]_PORT_A_write_enable_reg, , , , D1_q_a[11]_clock_0, , , , , );
D1_q_a[11]_PORT_A_data_out_reg = DFFE(D1_q_a[11]_PORT_A_data_out, D1_q_a[11]_clock_0, , , );
D1_q_a[11] = D1_q_a[11]_PORT_A_data_out_reg[0];


--D1_q_a[12] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[12]
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[12]_PORT_A_data_in = ~GND;
D1_q_a[12]_PORT_A_data_in_reg = DFFE(D1_q_a[12]_PORT_A_data_in, D1_q_a[12]_clock_0, , , );
D1_q_a[12]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[12]_PORT_A_address_reg = DFFE(D1_q_a[12]_PORT_A_address, D1_q_a[12]_clock_0, , , );
D1_q_a[12]_PORT_B_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[12]_PORT_B_address_reg = DFFE(D1_q_a[12]_PORT_B_address, D1_q_a[12]_clock_0, , , );
D1_q_a[12]_PORT_A_write_enable = GND;
D1_q_a[12]_PORT_A_write_enable_reg = DFFE(D1_q_a[12]_PORT_A_write_enable, D1_q_a[12]_clock_0, , , );
D1_q_a[12]_clock_0 = sys_clk;
D1_q_a[12]_PORT_A_data_out = MEMORY(D1_q_a[12]_PORT_A_data_in_reg, , D1_q_a[12]_PORT_A_address_reg, D1_q_a[12]_PORT_B_address_reg, D1_q_a[12]_PORT_A_write_enable_reg, , , , D1_q_a[12]_clock_0, , , , , );
D1_q_a[12]_PORT_A_data_out_reg = DFFE(D1_q_a[12]_PORT_A_data_out, D1_q_a[12]_clock_0, , , );
D1_q_a[12] = D1_q_a[12]_PORT_A_data_out_reg[0];


--D1_q_a[13] is sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[13]
--RAM Block Operation Mode: Single Port
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 14
--Port A Input: Registered, Port A Output: Registered
D1_q_a[13]_PORT_A_data_in = ~GND;
D1_q_a[13]_PORT_A_data_in_reg = DFFE(D1_q_a[13]_PORT_A_data_in, D1_q_a[13]_clock_0, , , );
D1_q_a[13]_PORT_A_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[13]_PORT_A_address_reg = DFFE(D1_q_a[13]_PORT_A_address, D1_q_a[13]_clock_0, , , );
D1_q_a[13]_PORT_B_address = BUS(A1L5Q, A1L9Q, A1L13Q, A1L17Q, A1L21Q, A1L25Q, A1L29Q, A1L33Q, A1L37Q, A1L41Q);
D1_q_a[13]_PORT_B_address_reg = DFFE(D1_q_a[13]_PORT_B_address, D1_q_a[13]_clock_0, , , );
D1_q_a[13]_PORT_A_write_enable = GND;
D1_q_a[13]_PORT_A_write_enable_reg = DFFE(D1_q_a[13]_PORT_A_write_enable, D1_q_a[13]_clock_0, , , );
D1_q_a[13]_clock_0 = sys_clk;