📄 sintab_altera.vwf

📁 在利用Verilog在FPGA平台上输出正弦波
💻 VWF
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TRANSITION_LIST("sin_output[7]")
{
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		LEVEL 1 FOR 5000.0;
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		LEVEL 1 FOR 10000.0;
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		LEVEL 1 FOR 5000.0;
		NODE
		{
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			LEVEL 1 FOR 4000.0;
		}
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		{
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			LEVEL 0 FOR 4000.0;
			LEVEL 1 FOR 4000.0;
		}
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		{
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			LEVEL 0 FOR 4000.0;
			LEVEL 1 FOR 3000.0;
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		{
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		NODE
		{
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			LEVEL 0 FOR 3000.0;
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			LEVEL 1 FOR 3000.0;
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			LEVEL 1 FOR 2000.0;
		}
		LEVEL 0 FOR 3000.0;
		LEVEL 1 FOR 2000.0;
		LEVEL 0 FOR 3000.0;
		NODE
		{
			REPEAT = 4;
			LEVEL 1 FOR 3000.0;
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		}
		LEVEL 1 FOR 3000.0;
		NODE
		{
			REPEAT = 5;
			LEVEL 0 FOR 3000.0;
			LEVEL 1 FOR 2000.0;
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		{
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			LEVEL 1 FOR 3000.0;
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		{
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			LEVEL 1 FOR 3000.0;
			LEVEL 0 FOR 3000.0;
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		LEVEL 1 FOR 3000.0;
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		LEVEL 1 FOR 12000.0;
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		LEVEL 1 FOR 7000.0;
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		LEVEL 0 FOR 5000.0;
		NODE
		{
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			LEVEL 1 FOR 5000.0;
			LEVEL 0 FOR 4000.0;
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		{
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			LEVEL 0 FOR 4000.0;
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		{
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			LEVEL 1 FOR 4000.0;
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		LEVEL 1 FOR 3000.0;
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		{
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		{
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			LEVEL 1 FOR 3000.0;
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		LEVEL 1 FOR 3000.0;
		NODE
		{
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			LEVEL 0 FOR 3000.0;
			LEVEL 1 FOR 2000.0;
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		LEVEL 0 FOR 3000.0;
		NODE
		{
			REPEAT = 5;
			LEVEL 1 FOR 3000.0;
			LEVEL 0 FOR 2000.0;
		}
		LEVEL 1 FOR 3000.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 3000.0;
			LEVEL 1 FOR 2000.0;
		}
		LEVEL 0 FOR 3000.0;
		LEVEL 1 FOR 3000.0;
		LEVEL 0 FOR 2000.0;
		LEVEL 1 FOR 3000.0;
		LEVEL 0 FOR 3000.0;
		LEVEL 1 FOR 2000.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 3000.0;
			LEVEL 1 FOR 3000.0;
			LEVEL 0 FOR 2000.0;
			LEVEL 1 FOR 3000.0;
		}
		NODE
		{
			REPEAT = 5;
			LEVEL 0 FOR 3000.0;
			LEVEL 1 FOR 3000.0;
		}
		LEVEL 0 FOR 3000.0;
		LEVEL 1 FOR 4000.0;
		LEVEL 0 FOR 3000.0;
		NODE
		{
			REPEAT = 3;
			LEVEL 1 FOR 3000.0;
			LEVEL 0 FOR 4000.0;
		}
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 4000.0;
			LEVEL 0 FOR 4000.0;
		}
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 4000.0;
			LEVEL 0 FOR 5000.0;
		}
		LEVEL 1 FOR 5000.0;
		LEVEL 0 FOR 6000.0;
		LEVEL 1 FOR 5000.0;
		LEVEL 0 FOR 7000.0;
		LEVEL 1 FOR 7000.0;
		LEVEL 0 FOR 7000.0;
		LEVEL 1 FOR 10000.0;
		LEVEL 0 FOR 12000.0;
		LEVEL 1 FOR 57000.0;
		LEVEL 0 FOR 12000.0;
		LEVEL 1 FOR 10000.0;
		LEVEL 0 FOR 7000.0;
		LEVEL 1 FOR 7000.0;
		LEVEL 0 FOR 7000.0;
		LEVEL 1 FOR 5000.0;
		LEVEL 0 FOR 6000.0;
		LEVEL 1 FOR 5000.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 5000.0;
			LEVEL 1 FOR 4000.0;
		}
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 4000.0;
			LEVEL 1 FOR 4000.0;
		}
		NODE
		{
			REPEAT = 3;
			LEVEL 0 FOR 4000.0;
			LEVEL 1 FOR 3000.0;
		}
		LEVEL 0 FOR 3000.0;
		LEVEL 1 FOR 4000.0;
		NODE
		{
			REPEAT = 6;
			LEVEL 0 FOR 3000.0;
			LEVEL 1 FOR 3000.0;
		}
		LEVEL 0 FOR 2000.0;
		LEVEL 1 FOR 3000.0;
		NODE
		{
			REPEAT = 2;
上一页 1 2 3 45
💿 文件大小 493 K
👤 上传用户 shsy22
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#Verilog #FPGA #输出 #正弦波
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