add_sub_enh.tdf

用verilog hdl硬件描述语言实现多人抢答器功能

--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=32 DEVICE_FAMILY="FLEX10K" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=7 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
--VERSION_BEGIN 6.0 cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ  VERSION_END


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--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION carry_sum (cin, sin)
RETURNS ( cout, sout);

--synthesis_resources = lut 8 
SUBDESIGN add_sub_enh
( 
	cin	:	input;
	dataa[6..0]	:	input;
	datab[6..0]	:	input;
	result[6..0]	:	output;
) 
VARIABLE 
	add_sub_cella[6..0] : carry_sum;
	external_cin_cell : carry_sum;
	datab_node[6..0]	: WIRE;
	main_cin_wire	: WIRE;

BEGIN 
	add_sub_cella[].cin = ( ((dataa[6..6] & datab_node[6..6]) # ((dataa[6..6] # datab_node[6..6]) & add_sub_cella[5].cout)), ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire)));
	add_sub_cella[].sin = ( ((dataa[6..6] $ datab_node[6..6]) $ add_sub_cella[5].cout), ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire));
	external_cin_cell.cin = cin;
	external_cin_cell.sin = B"0";
	datab_node[] = datab[];
	main_cin_wire = external_cin_cell.cout;
	result[] = add_sub_cella[].sout;
END;
--VALID FILE