qiangdaqi.fit.summary

来自「用verilog hdl硬件描述语言实现多人抢答器功能」· SUMMARY 代码 · 共 11 行

Fitter Status : Successful - Thu Jun 28 00:06:23 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : qiangdaqi
Top-level Entity Name : qiangda
Family : FLEX10K
Device : EPF10K10LC84-4
Timing Models : Final
Total logic elements : 45 / 576 ( 8 % )
Total pins : 12 / 59 ( 20 % )
Total memory bits : 0 / 6,144 ( 0 % )