qiangdaqi.tan.qmsg

用verilog hdl硬件描述语言实现多人抢答器功能

{ "Info" "ITDB_TSU_RESULT" "result4~reg0 k2 clk1 14.400 ns register " "Info: tsu for register \"result4~reg0\" (data pin = \"k2\", clock pin = \"clk1\") is 14.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.900 ns + Longest pin register " "Info: + Longest pin to register delay is 19.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns k2 1 PIN PIN_18 8 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_18; Fanout = 8; PIN Node = 'k2'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "" { k2 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.100 ns) + CELL(2.300 ns) 11.900 ns result4~338 2 COMB LC6_B17 2 " "Info: 2: + IC(6.100 ns) + CELL(2.300 ns) = 11.900 ns; Loc. = LC6_B17; Fanout = 2; COMB Node = 'result4~338'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "8.400 ns" { k2 result4~338 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 14.800 ns result4~339 3 COMB LC7_B17 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 14.800 ns; Loc. = LC7_B17; Fanout = 1; COMB Node = 'result4~339'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "2.900 ns" { result4~338 result4~339 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 16.600 ns result4~351 4 COMB LC4_B17 1 " "Info: 4: + IC(0.600 ns) + CELL(1.200 ns) = 16.600 ns; Loc. = LC4_B17; Fanout = 1; COMB Node = 'result4~351'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "1.800 ns" { result4~339 result4~351 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 18.100 ns result4~343 5 COMB LC5_B17 1 " "Info: 5: + IC(0.000 ns) + CELL(1.500 ns) = 18.100 ns; Loc. = LC5_B17; Fanout = 1; COMB Node = 'result4~343'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "1.500 ns" { result4~351 result4~343 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 19.900 ns result4~reg0 6 REG LC8_B17 4 " "Info: 6: + IC(0.600 ns) + CELL(1.200 ns) = 19.900 ns; Loc. = LC8_B17; Fanout = 4; REG Node = 'result4~reg0'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "1.800 ns" { result4~343 result4~reg0 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.000 ns ( 60.30 % ) " "Info: Total cell delay = 12.000 ns ( 60.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.900 ns ( 39.70 % ) " "Info: Total interconnect delay = 7.900 ns ( 39.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "19.900 ns" { k2 result4~338 result4~339 result4~351 result4~343 result4~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "19.900 ns" { k2 k2~out result4~338 result4~339 result4~351 result4~343 result4~reg0 } { 0.000ns 0.000ns 6.100ns 0.600ns 0.600ns 0.000ns 0.600ns } { 0.000ns 3.500ns 2.300ns 2.300ns 1.200ns 1.500ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 44 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 8.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk1\" to destination register is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk1 1 CLK PIN_3 21 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_3; Fanout = 21; CLK Node = 'clk1'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(0.000 ns) 8.000 ns result4~reg0 2 REG LC8_B17 4 " "Info: 2: + IC(4.500 ns) + CELL(0.000 ns) = 8.000 ns; Loc. = LC8_B17; Fanout = 4; REG Node = 'result4~reg0'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "4.500 ns" { clk1 result4~reg0 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 43.75 % ) " "Info: Total cell delay = 3.500 ns ( 43.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.500 ns ( 56.25 % ) " "Info: Total interconnect delay = 4.500 ns ( 56.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "8.000 ns" { clk1 result4~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "8.000 ns" { clk1 clk1~out result4~reg0 } { 0.000ns 0.000ns 4.500ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "19.900 ns" { k2 result4~338 result4~339 result4~351 result4~343 result4~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "19.900 ns" { k2 k2~out result4~338 result4~339 result4~351 result4~343 result4~reg0 } { 0.000ns 0.000ns 6.100ns 0.600ns 0.600ns 0.000ns 0.600ns } { 0.000ns 3.500ns 2.300ns 2.300ns 1.200ns 1.500ns 1.200ns } } } { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "8.000 ns" { clk1 result4~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "8.000 ns" { clk1 clk1~out result4~reg0 } { 0.000ns 0.000ns 4.500ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk1 alarm alarm_delay 17.900 ns register " "Info: tco from clock \"clk1\" to destination pin \"alarm\" through register \"alarm_delay\" is 17.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 7.800 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to source register is 7.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk1 1 CLK PIN_3 21 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_3; Fanout = 21; CLK Node = 'clk1'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(0.000 ns) 7.800 ns alarm_delay 2 REG LC1_B14 1 " "Info: 2: + IC(4.300 ns) + CELL(0.000 ns) = 7.800 ns; Loc. = LC1_B14; Fanout = 1; REG Node = 'alarm_delay'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "4.300 ns" { clk1 alarm_delay } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 44.87 % ) " "Info: Total cell delay = 3.500 ns ( 44.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 55.13 % ) " "Info: Total interconnect delay = 4.300 ns ( 55.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "7.800 ns" { clk1 alarm_delay } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "7.800 ns" { clk1 clk1~out alarm_delay } { 0.000ns 0.000ns 4.300ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 31 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register pin " "Info: + Longest register to pin delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns alarm_delay 1 REG LC1_B14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B14; Fanout = 1; REG Node = 'alarm_delay'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "" { alarm_delay } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns alarm~2 2 COMB LC8_B14 1 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC8_B14; Fanout = 1; COMB Node = 'alarm~2'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "2.900 ns" { alarm_delay alarm~2 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.100 ns) 9.000 ns alarm 3 PIN PIN_83 0 " "Info: 3: + IC(1.000 ns) + CELL(5.100 ns) = 9.000 ns; Loc. = PIN_83; Fanout = 0; PIN Node = 'alarm'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "6.100 ns" { alarm~2 alarm } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns ( 82.22 % ) " "Info: Total cell delay = 7.400 ns ( 82.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 17.78 % ) " "Info: Total interconnect delay = 1.600 ns ( 17.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "9.000 ns" { alarm_delay alarm~2 alarm } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "9.000 ns" { alarm_delay alarm~2 alarm } { 0.000ns 0.600ns 1.000ns } { 0.000ns 2.300ns 5.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "7.800 ns" { clk1 alarm_delay } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "7.800 ns" { clk1 clk1~out alarm_delay } { 0.000ns 0.000ns 4.300ns } { 0.000ns 3.500ns 0.000ns } } } { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "9.000 ns" { alarm_delay alarm~2 alarm } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "9.000 ns" { alarm_delay alarm~2 alarm } { 0.000ns 0.600ns 1.000ns } { 0.000ns 2.300ns 5.100ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk2 alarm 15.300 ns Longest " "Info: Longest tpd from source pin \"clk2\" to destination pin \"alarm\" is 15.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk2 1 CLK PIN_6 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_6; Fanout = 2; CLK Node = 'clk2'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(1.800 ns) 9.200 ns alarm~2 2 COMB LC8_B14 1 " "Info: 2: + IC(3.900 ns) + CELL(1.800 ns) = 9.200 ns; Loc. = LC8_B14; Fanout = 1; COMB Node = 'alarm~2'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "5.700 ns" { clk2 alarm~2 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.100 ns) 15.300 ns alarm 3 PIN PIN_83 0 " "Info: 3: + IC(1.000 ns) + CELL(5.100 ns) = 15.300 ns; Loc. = PIN_83; Fanout = 0; PIN Node = 'alarm'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "6.100 ns" { alarm~2 alarm } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.400 ns ( 67.97 % ) " "Info: Total cell delay = 10.400 ns ( 67.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns ( 32.03 % ) " "Info: Total interconnect delay = 4.900 ns ( 32.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "15.300 ns" { clk2 alarm~2 alarm } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "15.300 ns" { clk2 clk2~out alarm~2 alarm } { 0.000ns 0.000ns 3.900ns 1.000ns } { 0.000ns 3.500ns 1.800ns 5.100ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "result3~reg0 k3 clk1 -1.700 ns register " "Info: th for register \"result3~reg0\" (data pin = \"k3\", clock pin = \"clk1\") is -1.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 8.000 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to destination register is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk1 1 CLK PIN_3 21 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_3; Fanout = 21; CLK Node = 'clk1'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(0.000 ns) 8.000 ns result3~reg0 2 REG LC1_B16 4 " "Info: 2: + IC(4.500 ns) + CELL(0.000 ns) = 8.000 ns; Loc. = LC1_B16; Fanout = 4; REG Node = 'result3~reg0'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "4.500 ns" { clk1 result3~reg0 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 43.75 % ) " "Info: Total cell delay = 3.500 ns ( 43.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.500 ns ( 56.25 % ) " "Info: Total interconnect delay = 4.500 ns ( 56.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "8.000 ns" { clk1 result3~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "8.000 ns" { clk1 clk1~out result3~reg0 } { 0.000ns 0.000ns 4.500ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 44 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.300 ns - Shortest pin register " "Info: - Shortest pin to register delay is 11.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns k3 1 PIN PIN_17 7 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_17; Fanout = 7; PIN Node = 'k3'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "" { k3 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.100 ns) + CELL(1.700 ns) 11.300 ns result3~reg0 2 REG LC1_B16 4 " "Info: 2: + IC(6.100 ns) + CELL(1.700 ns) = 11.300 ns; Loc. = LC1_B16; Fanout = 4; REG Node = 'result3~reg0'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "7.800 ns" { k3 result3~reg0 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns ( 46.02 % ) " "Info: Total cell delay = 5.200 ns ( 46.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.100 ns ( 53.98 % ) " "Info: Total interconnect delay = 6.100 ns ( 53.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "11.300 ns" { k3 result3~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "11.300 ns" { k3 k3~out result3~reg0 } { 0.000ns 0.000ns 6.100ns } { 0.000ns 3.500ns 1.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "8.000 ns" { clk1 result3~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "8.000 ns" { clk1 clk1~out result3~reg0 } { 0.000ns 0.000ns 4.500ns } { 0.000ns 3.500ns 0.000ns } } } { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "11.300 ns" { k3 result3~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "11.300 ns" { k3 k3~out result3~reg0 } { 0.000ns 0.000ns 6.100ns } { 0.000ns 3.500ns 1.700ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}