qiangdaqi.tan.qmsg

用verilog hdl硬件描述语言实现多人抢答器功能

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" {  } { { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 20 -1 0 } } { "d:/program files/altera/quartus 6.0/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus 6.0/win/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk2 " "Info: Assuming node \"clk2\" is an undefined clock" {  } { { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 21 -1 0 } } { "d:/program files/altera/quartus 6.0/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus 6.0/win/Assignment Editor.qase" 1 { { 0 "clk2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] register alarm_ahead 41.84 MHz 23.9 ns Internal " "Info: Clock \"clk1\" has Internal fmax of 41.84 MHz between source register \"lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]\" and destination register \"alarm_ahead\" (period= 23.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.200 ns + Longest register register " "Info: + Longest register to register delay is 20.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 1 REG LC8_B15 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B15; Fanout = 2; REG Node = 'lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/quartus 6.0/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 4.500 ns Equal0~73 2 COMB LC4_B13 2 " "Info: 2: + IC(2.200 ns) + CELL(2.300 ns) = 4.500 ns; Loc. = LC4_B13; Fanout = 2; COMB Node = 'Equal0~73'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "4.500 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] Equal0~73 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 7.400 ns _~26 3 COMB LC1_B13 14 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 7.400 ns; Loc. = LC1_B13; Fanout = 14; COMB Node = '_~26'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "2.900 ns" { Equal0~73 _~26 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(2.300 ns) 12.200 ns result4~332 4 COMB LC1_B17 6 " "Info: 4: + IC(2.500 ns) + CELL(2.300 ns) = 12.200 ns; Loc. = LC1_B17; Fanout = 6; COMB Node = 'result4~332'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "4.800 ns" { _~26 result4~332 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(2.300 ns) 16.800 ns alarm_ahead~88 5 COMB LC4_B16 3 " "Info: 5: + IC(2.300 ns) + CELL(2.300 ns) = 16.800 ns; Loc. = LC4_B16; Fanout = 3; COMB Node = 'alarm_ahead~88'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "4.600 ns" { result4~332 alarm_ahead~88 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 20.200 ns alarm_ahead 6 REG LC2_B14 1 " "Info: 6: + IC(2.200 ns) + CELL(1.200 ns) = 20.200 ns; Loc. = LC2_B14; Fanout = 1; REG Node = 'alarm_ahead'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "3.400 ns" { alarm_ahead~88 alarm_ahead } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.400 ns ( 51.49 % ) " "Info: Total cell delay = 10.400 ns ( 51.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.800 ns ( 48.51 % ) " "Info: Total interconnect delay = 9.800 ns ( 48.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "20.200 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] Equal0~73 _~26 result4~332 alarm_ahead~88 alarm_ahead } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "20.200 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] Equal0~73 _~26 result4~332 alarm_ahead~88 alarm_ahead } { 0.000ns 2.200ns 0.600ns 2.500ns 2.300ns 2.200ns } { 0.000ns 2.300ns 2.300ns 2.300ns 2.300ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.100 ns - Smallest " "Info: - Smallest clock skew is -0.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 7.800 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1\" to destination register is 7.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk1 1 CLK PIN_3 21 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_3; Fanout = 21; CLK Node = 'clk1'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(0.000 ns) 7.800 ns alarm_ahead 2 REG LC2_B14 1 " "Info: 2: + IC(4.300 ns) + CELL(0.000 ns) = 7.800 ns; Loc. = LC2_B14; Fanout = 1; REG Node = 'alarm_ahead'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "4.300 ns" { clk1 alarm_ahead } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 44.87 % ) " "Info: Total cell delay = 3.500 ns ( 44.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 55.13 % ) " "Info: Total interconnect delay = 4.300 ns ( 55.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "7.800 ns" { clk1 alarm_ahead } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "7.800 ns" { clk1 clk1~out alarm_ahead } { 0.000ns 0.000ns 4.300ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 7.900 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 7.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk1 1 CLK PIN_3 21 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_3; Fanout = 21; CLK Node = 'clk1'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.400 ns) + CELL(0.000 ns) 7.900 ns lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 2 REG LC8_B15 2 " "Info: 2: + IC(4.400 ns) + CELL(0.000 ns) = 7.900 ns; Loc. = LC8_B15; Fanout = 2; REG Node = 'lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "4.400 ns" { clk1 lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/quartus 6.0/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 44.30 % ) " "Info: Total cell delay = 3.500 ns ( 44.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.400 ns ( 55.70 % ) " "Info: Total interconnect delay = 4.400 ns ( 55.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "7.900 ns" { clk1 lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "7.900 ns" { clk1 clk1~out lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 4.400ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "7.800 ns" { clk1 alarm_ahead } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "7.800 ns" { clk1 clk1~out alarm_ahead } { 0.000ns 0.000ns 4.300ns } { 0.000ns 3.500ns 0.000ns } } } { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "7.900 ns" { clk1 lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "7.900 ns" { clk1 clk1~out lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 4.400ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/quartus 6.0/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 30 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "20.200 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] Equal0~73 _~26 result4~332 alarm_ahead~88 alarm_ahead } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "20.200 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] Equal0~73 _~26 result4~332 alarm_ahead~88 alarm_ahead } { 0.000ns 2.200ns 0.600ns 2.500ns 2.300ns 2.200ns } { 0.000ns 2.300ns 2.300ns 2.300ns 2.300ns 1.200ns } } } { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "7.800 ns" { clk1 alarm_ahead } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "7.800 ns" { clk1 clk1~out alarm_ahead } { 0.000ns 0.000ns 4.300ns } { 0.000ns 3.500ns 0.000ns } } } { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "7.900 ns" { clk1 lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "7.900 ns" { clk1 clk1~out lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 4.400ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk2 register register clk3 clk3 125.0 MHz Internal " "Info: Clock \"clk2\" Internal fmax is restricted to 125.0 MHz between source register \"clk3\" and destination register \"clk3\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.800 ns + Longest register register " "Info: + Longest register to register delay is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk3 1 REG LC3_B14 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B14; Fanout = 2; REG Node = 'clk3'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "" { clk3 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 1.800 ns clk3 2 REG LC3_B14 2 " "Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC3_B14; Fanout = 2; REG Node = 'clk3'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk3 clk3 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns ( 66.67 % ) " "Info: Total cell delay = 1.200 ns ( 66.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 33.33 % ) " "Info: Total interconnect delay = 0.600 ns ( 33.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk3 clk3 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "1.800 ns" { clk3 clk3 } { 0.000ns 0.600ns } { 0.000ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 destination 7.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk2\" to destination register is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk2 1 CLK PIN_6 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_6; Fanout = 2; CLK Node = 'clk2'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(0.000 ns) 7.400 ns clk3 2 REG LC3_B14 2 " "Info: 2: + IC(3.900 ns) + CELL(0.000 ns) = 7.400 ns; Loc. = LC3_B14; Fanout = 2; REG Node = 'clk3'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "3.900 ns" { clk2 clk3 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 47.30 % ) " "Info: Total cell delay = 3.500 ns ( 47.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns ( 52.70 % ) " "Info: Total interconnect delay = 3.900 ns ( 52.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "7.400 ns" { clk2 clk3 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "7.400 ns" { clk2 clk2~out clk3 } { 0.000ns 0.000ns 3.900ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 source 7.400 ns - Longest register " "Info: - Longest clock path from clock \"clk2\" to source register is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk2 1 CLK PIN_6 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_6; Fanout = 2; CLK Node = 'clk2'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(0.000 ns) 7.400 ns clk3 2 REG LC3_B14 2 " "Info: 2: + IC(3.900 ns) + CELL(0.000 ns) = 7.400 ns; Loc. = LC3_B14; Fanout = 2; REG Node = 'clk3'" {  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "3.900 ns" { clk2 clk3 } "NODE_NAME" } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 47.30 % ) " "Info: Total cell delay = 3.500 ns ( 47.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns ( 52.70 % ) " "Info: Total interconnect delay = 3.900 ns ( 52.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "7.400 ns" { clk2 clk3 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "7.400 ns" { clk2 clk2~out clk3 } { 0.000ns 0.000ns 3.900ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "7.400 ns" { clk2 clk3 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "7.400 ns" { clk2 clk2~out clk3 } { 0.000ns 0.000ns 3.900ns } { 0.000ns 3.500ns 0.000ns } } } { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "7.400 ns" { clk2 clk3 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "7.400 ns" { clk2 clk2~out clk3 } { 0.000ns 0.000ns 3.900ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 36 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk3 clk3 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "1.800 ns" { clk3 clk3 } { 0.000ns 0.600ns } { 0.000ns 1.200ns } } } { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "7.400 ns" { clk2 clk3 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "7.400 ns" { clk2 clk2~out clk3 } { 0.000ns 0.000ns 3.900ns } { 0.000ns 3.500ns 0.000ns } } } { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "7.400 ns" { clk2 clk3 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "7.400 ns" { clk2 clk2~out clk3 } { 0.000ns 0.000ns 3.900ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus 6.0/win/TimingClosureFloorplan.fld" "" "" { clk3 } "NODE_NAME" } } { "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus 6.0/win/Technology_Viewer.qrui" "" { clk3 } {  } {  } } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 36 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}