qiangdaqi.map.qmsg

用verilog hdl硬件描述语言实现多人抢答器功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 28 00:09:07 2007 " "Info: Processing started: Thu Jun 28 00:09:07 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off qiangdaqi -c qiangdaqi " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off qiangdaqi -c qiangdaqi" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "qiangda.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file qiangda.v" { { "Info" "ISGN_ENTITY_NAME" "1 qiangda " "Info: Found entity 1: qiangda" {  } { { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "score.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file score.v" { { "Info" "ISGN_ENTITY_NAME" "1 score " "Info: Found entity 1: score" {  } { { "score.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/score.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "qiangdaqi.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file qiangdaqi.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 qiangdaqi " "Info: Found entity 1: qiangdaqi" {  } { { "qiangdaqi.bdf" "" { Schematic "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangdaqi.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "qiangdaqi " "Info: Elaborating entity \"qiangdaqi\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "qiangda qiangda:inst2 " "Info: Elaborating entity \"qiangda\" for hierarchy \"qiangda:inst2\"" {  } { { "qiangdaqi.bdf" "inst2" { Schematic "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangdaqi.bdf" { { -1008 160 272 -848 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "score score:inst " "Info: Elaborating entity \"score\" for hierarchy \"score:inst\"" {  } { { "qiangdaqi.bdf" "inst" { Schematic "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangdaqi.bdf" { { -1072 344 488 -880 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "qiangda:inst2\|cnt\[0\]~8 8 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: \"qiangda:inst2\|cnt\[0\]~8\"" {  } { { "qiangda.v" "cnt\[0\]~8" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 44 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus 6.0/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus 6.0/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/program files/altera/quartus 6.0/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "qiangda:inst2\|lpm_counter:cnt_rtl_0 " "Info: Elaborated megafunction instantiation \"qiangda:inst2\|lpm_counter:cnt_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus 6.0/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus 6.0/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/quartus 6.0/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "qiangda:inst2\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter qiangda:inst2\|lpm_counter:cnt_rtl_0 " "Info: Elaborated megafunction instantiation \"qiangda:inst2\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\", which is child of megafunction instantiation \"qiangda:inst2\|lpm_counter:cnt_rtl_0\"" {  } { { "lpm_counter.tdf" "" { Text "d:/program files/altera/quartus 6.0/libraries/megafunctions/lpm_counter.tdf" 410 4 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "qiangda:inst2\|lpm_counter:cnt_rtl_0 " "Info: Instantiated megafunction \"qiangda:inst2\|lpm_counter:cnt_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "score.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/score.v" 40 -1 0 } } { "score.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/score.v" 40 -1 0 } } { "score.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/score.v" 40 -1 0 } } { "score.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/score.v" 40 -1 0 } } { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 29 -1 0 } } { "score.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/score.v" 29 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "225 " "Info: Implemented 225 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "37 " "Info: Implemented 37 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "178 " "Info: Implemented 178 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 28 00:09:10 2007 " "Info: Processing ended: Thu Jun 28 00:09:10 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}