qiangdaqi.fnsim.qmsg

用verilog hdl硬件描述语言实现多人抢答器功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 28 00:10:26 2007 " "Info: Processing started: Thu Jun 28 00:10:26 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off qiangdaqi -c qiangdaqi --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off qiangdaqi -c qiangdaqi --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "qiangda.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file qiangda.v" { { "Info" "ISGN_ENTITY_NAME" "1 qiangda " "Info: Found entity 1: qiangda" {  } { { "qiangda.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangda.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "score.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file score.v" { { "Info" "ISGN_ENTITY_NAME" "1 score " "Info: Found entity 1: score" {  } { { "score.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/score.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "qiangdaqi.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file qiangdaqi.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 qiangdaqi " "Info: Found entity 1: qiangdaqi" {  } { { "qiangdaqi.bdf" "" { Schematic "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangdaqi.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "qiangdaqi " "Info: Elaborating entity \"qiangdaqi\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "qiangda qiangda:inst2 " "Info: Elaborating entity \"qiangda\" for hierarchy \"qiangda:inst2\"" {  } { { "qiangdaqi.bdf" "inst2" { Schematic "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangdaqi.bdf" { { -1008 160 272 -848 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "score score:inst " "Info: Elaborating entity \"score\" for hierarchy \"score:inst\"" {  } { { "qiangdaqi.bdf" "inst" { Schematic "E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangdaqi.bdf" { { -1072 344 488 -880 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus 6.0/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus 6.0/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/program files/altera/quartus 6.0/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "score:inst\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"score:inst\|lpm_add_sub:Add0\"" {  } { { "score.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/score.v" 53 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus 6.0/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus 6.0/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/program files/altera/quartus 6.0/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "score:inst\|lpm_add_sub:Add0\|addcore:adder score:inst\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"score:inst\|lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"score:inst\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "d:/program files/altera/quartus 6.0/libraries/megafunctions/lpm_add_sub.tdf" 266 4 0 } } { "score.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/score.v" 53 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "score:inst\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"score:inst\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "score.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/score.v" 53 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus 6.0/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus 6.0/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus 6.0/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "score:inst\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node score:inst\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"score:inst\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"score:inst\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "d:/program files/altera/quartus 6.0/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "score.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/score.v" 53 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "score:inst\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"score:inst\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "score.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/score.v" 53 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "score:inst\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node score:inst\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"score:inst\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"score:inst\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "d:/program files/altera/quartus 6.0/libraries/megafunctions/addcore.tdf" 120 6 0 } } { "score.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/score.v" 53 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "score:inst\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"score:inst\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "score.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/score.v" 53 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus 6.0/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus 6.0/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/program files/altera/quartus 6.0/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "score:inst\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs score:inst\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"score:inst\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"score:inst\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "d:/program files/altera/quartus 6.0/libraries/megafunctions/lpm_add_sub.tdf" 284 2 0 } } { "score.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/score.v" 53 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "score:inst\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"score:inst\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "score.v" "" { Text "E:/Programs/Verilog/workspace/qiangdaqi(auto)/score.v" 53 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}