qiangdaqi.fit.rpt

用verilog hdl硬件描述语言实现多人抢答器功能

; 13                         ; 1              ;
+----------------------------+----------------+


+----------------------------------------------------------------------------------------+
; Row Interconnect                                                                       ;
+-------+-------------------+-----------------------------+------------------------------+
; Row   ; Interconnect Used ; Left Half Interconnect Used ; Right Half Interconnect Used ;
+-------+-------------------+-----------------------------+------------------------------+
;  A    ;  4 / 96 ( 4 % )   ;  0 / 48 ( 0 % )             ;  0 / 48 ( 0 % )              ;
;  B    ;  6 / 96 ( 6 % )   ;  0 / 48 ( 0 % )             ;  25 / 48 ( 52 % )            ;
;  C    ;  0 / 96 ( 0 % )   ;  0 / 48 ( 0 % )             ;  0 / 48 ( 0 % )              ;
; Total ;  10 / 288 ( 3 % ) ;  0 / 144 ( 0 % )            ;  25 / 144 ( 17 % )           ;
+-------+-------------------+-----------------------------+------------------------------+


+---------------------------+
; LAB Column Interconnect   ;
+-------+-------------------+
; Col.  ; Interconnect Used ;
+-------+-------------------+
; 1     ;  0 / 24 ( 0 % )   ;
; 2     ;  0 / 24 ( 0 % )   ;
; 3     ;  1 / 24 ( 4 % )   ;
; 4     ;  1 / 24 ( 4 % )   ;
; 5     ;  0 / 24 ( 0 % )   ;
; 6     ;  0 / 24 ( 0 % )   ;
; 7     ;  0 / 24 ( 0 % )   ;
; 8     ;  0 / 24 ( 0 % )   ;
; 9     ;  0 / 24 ( 0 % )   ;
; 10    ;  0 / 24 ( 0 % )   ;
; 11    ;  0 / 24 ( 0 % )   ;
; 12    ;  1 / 24 ( 4 % )   ;
; 13    ;  1 / 24 ( 4 % )   ;
; 14    ;  1 / 24 ( 4 % )   ;
; 15    ;  1 / 24 ( 4 % )   ;
; 16    ;  0 / 24 ( 0 % )   ;
; 17    ;  1 / 24 ( 4 % )   ;
; 18    ;  1 / 24 ( 4 % )   ;
; 19    ;  0 / 24 ( 0 % )   ;
; 20    ;  0 / 24 ( 0 % )   ;
; 21    ;  0 / 24 ( 0 % )   ;
; 22    ;  0 / 24 ( 0 % )   ;
; 23    ;  0 / 24 ( 0 % )   ;
; 24    ;  0 / 24 ( 0 % )   ;
; Total ;  8 / 576 ( 1 % )  ;
+-------+-------------------+


+---------------------------+
; LAB Column Interconnect   ;
+-------+-------------------+
; Col.  ; Interconnect Used ;
+-------+-------------------+
; 1     ;  0 / 24 ( 0 % )   ;
; Total ;  0 / 24 ( 0 % )   ;
+-------+-------------------+


+-------------------------------------------------------+
; Fitter Resource Usage Summary                         ;
+-----------------------------------+-------------------+
; Resource                          ; Usage             ;
+-----------------------------------+-------------------+
; Registers                         ; 20 / 576 ( 3 % )  ;
; Total LABs                        ; 0 / 72 ( 0 % )    ;
; Logic elements in carry chains    ; 8                 ;
; User inserted logic elements      ; 0                 ;
; I/O pins                          ; 12 / 59 ( 20 % )  ;
;     -- Clock pins                 ; 0 / 0 ( -- )      ;
;     -- Dedicated input pins       ; 0 / 4 ( 0 % )     ;
; Global signals                    ; 0                 ;
; EABs                              ; 0 / 3 ( 0 % )     ;
; Total memory bits                 ; 0 / 6,144 ( 0 % ) ;
; Total RAM block bits              ; 0 / 6,144 ( 0 % ) ;
; Maximum fan-out node              ; clk1              ;
; Maximum fan-out                   ; 19                ;
; Highest non-global fan-out signal ; clk1              ;
; Highest non-global fan-out        ; 19                ;
; Total fan-out                     ; 178               ;
; Average fan-out                   ; 3.12              ;
+-----------------------------------+-------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                                                                                                                                                                         ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------+
; Compilation Hierarchy Node             ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                           ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------+
; |qiangda                               ; 45 (37)     ; 20           ; 0           ; 12   ; 25 (25)      ; 1 (1)             ; 19 (11)          ; 8 (0)           ; 0 (0)      ; |qiangda                                                      ;
;    |lpm_counter:cnt_rtl_0|             ; 8 (0)       ; 8            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 8 (0)            ; 8 (0)           ; 0 (0)      ; |qiangda|lpm_counter:cnt_rtl_0                                ;
;       |alt_counter_f10ke:wysi_counter| ; 8 (8)       ; 8            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 8 (8)            ; 8 (8)           ; 0 (0)      ; |qiangda|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------+
; Delay Chain Summary              ;
+---------+----------+-------------+
; Name    ; Pin Type ; Pad to Core ;
+---------+----------+-------------+
; clk2    ; Input    ; OFF         ;
; clk1    ; Input    ; OFF         ;
; reset   ; Input    ; OFF         ;
; k1      ; Input    ; OFF         ;
; k2      ; Input    ; OFF         ;
; k3      ; Input    ; OFF         ;
; k4      ; Input    ; OFF         ;
; alarm   ; Output   ; OFF         ;
; result1 ; Output   ; OFF         ;
; result2 ; Output   ; OFF         ;
; result3 ; Output   ; OFF         ;
; result4 ; Output   ; OFF         ;
+---------+----------+-------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/Programs/Verilog/workspace/qiangdaqi(auto)/qiangdaqi.pin.


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Jun 28 00:06:17 2007
Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off qiangdaqi -c qiangdaqi
Info: Selected device EPF10K10LC84-4 for design "qiangdaqi"
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Inserted 0 logic cells in first fitting attempt
Warning: Ignored locations or region assignments to the following nodes
    Warning: Node "down" is assigned to location or region, but does not exist in design
    Warning: Node "led1" is assigned to location or region, but does not exist in design
    Warning: Node "led2" is assigned to location or region, but does not exist in design
    Warning: Node "led3" is assigned to location or region, but does not exist in design
    Warning: Node "led4" is assigned to location or region, but does not exist in design
    Warning: Node "reset1" is assigned to location or region, but does not exist in design
    Warning: Node "score1[0]" is assigned to location or region, but does not exist in design
    Warning: Node "score1[1]" is assigned to location or region, but does not exist in design
    Warning: Node "score1[2]" is assigned to location or region, but does not exist in design
    Warning: Node "score1[3]" is assigned to location or region, but does not exist in design
    Warning: Node "score1[4]" is assigned to location or region, but does not exist in design
    Warning: Node "score1[5]" is assigned to location or region, but does not exist in design
    Warning: Node "score1[6]" is assigned to location or region, but does not exist in design
    Warning: Node "score1[7]" is assigned to location or region, but does not exist in design
    Warning: Node "score2[0]" is assigned to location or region, but does not exist in design
    Warning: Node "score2[1]" is assigned to location or region, but does not exist in design
    Warning: Node "score2[2]" is assigned to location or region, but does not exist in design
    Warning: Node "score2[3]" is assigned to location or region, but does not exist in design
    Warning: Node "score2[4]" is assigned to location or region, but does not exist in design
    Warning: Node "score2[5]" is assigned to location or region, but does not exist in design
    Warning: Node "score2[6]" is assigned to location or region, but does not exist in design
    Warning: Node "score2[7]" is assigned to location or region, but does not exist in design
    Warning: Node "score3[0]" is assigned to location or region, but does not exist in design
    Warning: Node "score3[1]" is assigned to location or region, but does not exist in design
    Warning: Node "score3[2]" is assigned to location or region, but does not exist in design
    Warning: Node "score3[3]" is assigned to location or region, but does not exist in design
    Warning: Node "score3[4]" is assigned to location or region, but does not exist in design
    Warning: Node "score3[5]" is assigned to location or region, but does not exist in design
    Warning: Node "score3[6]" is assigned to location or region, but does not exist in design
    Warning: Node "score3[7]" is assigned to location or region, but does not exist in design
    Warning: Node "score4[0]" is assigned to location or region, but does not exist in design
    Warning: Node "score4[1]" is assigned to location or region, but does not exist in design
    Warning: Node "score4[2]" is assigned to location or region, but does not exist in design
    Warning: Node "score4[3]" is assigned to location or region, but does not exist in design
    Warning: Node "score4[4]" is assigned to location or region, but does not exist in design
    Warning: Node "score4[5]" is assigned to location or region, but does not exist in design
    Warning: Node "score4[6]" is assigned to location or region, but does not exist in design
    Warning: Node "score4[7]" is assigned to location or region, but does not exist in design
    Warning: Node "up" is assigned to location or region, but does not exist in design
Info: Started fitting attempt 1 on Thu Jun 28 2007 at 00:06:22
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Quartus II Fitter was successful. 0 errors, 40 warnings
    Info: Processing ended: Thu Jun 28 00:06:23 2007
    Info: Elapsed time: 00:00:06