score.v

用verilog hdl硬件描述语言实现多人抢答器功能

/*======================================================
= Module Neme:   score
=Project Name:   qiangdaqi
=      Vesion:   2007-6-26 Created By tmsonhust 
======================================================*/
module score(up,
             down,
             clk,
			 reset,
			 reset1,
             result1,
             result2,
             result3,
             result4,
             score1,
             score2,
             score3,
             score4);

input up ;  //加分信号
input down; //减分信号
input clk;   //时钟信号
input reset; //复位信号
input reset1; //初始分设置信号
input result1,result2,result3,result4;    //抢答结果输入
output [7:0] score1,score2,score3,score4;//各组得分

reg [7:0] score1,score2,score3,score4;
reg flag;  //防止按键一次加多下

always@(posedge clk or posedge reset1 or posedge reset)
if(reset1)
	begin
        	score1 <= 8'h10;
        	score2 <= 8'h10;
        	score3 <= 8'h10;
        	score4 <= 8'h10; 
			flag <= 1;
	end
else if(reset)
		flag <= 1;
else if(up)
	begin
		if(result1 == 1 && flag == 1)
			begin
				flag <= 0;
				if(score1[3:0] == 4'b1001)
					begin
						score1[3:0] <= 4'b0;
						if(score1[7:4]== 4'b1001)
							score1[7:4] <= 4'b0;
						else
							score1[7:4] <= score1[7:4] + 4'b1;
					end
				else
					score1[3:0] <= score1[3:0] + 4'b001;
			end

		if(result2 == 1 && flag == 1)
			begin
				flag <= 0;
				if(score2[3:0] == 4'b1001)
					begin
						score2[3:0] <= 4'b0;
						if(score2[7:4]==9)
							score2[7:4] <= 4'b0;
						else
							score2[7:4] <= score2[7:4] + 4'b1;
					end
				else
					score2[3:0] <= score2[3:0] + 4'b1;
			end

		if(result3 == 1 && flag == 1)
			begin
				flag <= 0;
				if(score3[3:0] == 4'b1001)
					begin
						score3[3:0] <= 4'b0;
						if(score3[7:4] == 4'b1001)
							score3[7:4] <= 4'b0;
						else
							score3[7:4] <= score3[7:4] + 4'b1;
					end
				else
					score3[3:0] <= score3[3:0] + 4'b1;
			end

		if(result4 == 1 && flag == 1)
			begin
				flag <= 0;
				if(score4[3:0] == 4'b1001)
					begin
						score4[3:0] <= 4'b0;
						if(score4[7:4] == 4'b1001)
							score4[7:4] <= 4'b0;
						else
							score4[7:4] <= score4[7:4] + 4'b1;
					end
				else
					score4[3:0] <= score4[3:0] + 4'b1;
			end
	end
else if(down)
	begin
		if(result1 == 1 && flag == 1)
			begin
				flag <= 0;
				if(score1[3:0] != 4'b0000)
					score1[3:0] <= score1[3:0] - 4'b1;
				else if(score1[7:4] != 4'b0000)
					begin
						score1[7:4] <= score1[7:4] - 4'b1;
						score1[3:0] <= 4'b1001;
					end     //高位低位都为0的话锁存，保持00不变
 			end

		if(result2 == 1 && flag == 1)
			begin
				flag <= 0;
				if(score2[3:0]!=4'b0000)
					score2[3:0] <= score2[3:0] - 4'b1;
				else if(score2[7:4]!=4'b0000)
					begin
						score2[7:4] <= score2[7:4] - 4'b1;
						score2[3:0] <= 9;
					end     //高位低位都为0的话锁存，保持00不变
 			end

		if(result3 == 1 && flag == 1)
			begin
				flag <= 0;
				if(score3[3:0]!=4'b0000)
					score3[3:0] <= score3[3:0] - 4'b1;
				else if(score3[7:4]!=4'b0000)
					begin
						score3[7:4] <= score3[7:4] - 4'b1;
						score3[3:0] <= 4'b1001;
					end     //高位低位都为0的话锁存，保持00不变
 			end

		if(result4 == 1 && flag == 1)
			begin
				flag <= 0;
				if(score4[3:0]!=4'b0000)
					score4[3:0] <= score4[3:0] - 4'b1;
				else if(score4[7:4]!=4'b0000)
					begin
						score4[7:4] <= score4[7:4] - 4'b1;
						score4[3:0] <= 4'b1001;
					end     //高位低位都为0的话锁存，保持00不变
 			end
end
endmodule