qiangdaqi.map.rpt

用verilog hdl硬件描述语言实现多人抢答器功能

; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 178     ;
; Total combinational functions     ; 169     ;
;     -- Total 4-input functions    ; 74      ;
;     -- Total 3-input functions    ; 45      ;
;     -- Total 2-input functions    ; 36      ;
;     -- Total 1-input functions    ; 8       ;
;     -- Total 0-input functions    ; 6       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 53      ;
; Total logic cells in carry chains ; 8       ;
; I/O pins                          ; 47      ;
; Maximum fan-out node              ; clk1    ;
; Maximum fan-out                   ; 52      ;
; Total fan-out                     ; 711     ;
; Average fan-out                   ; 3.16    ;
+-----------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                              ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------+
; Compilation Hierarchy Node                ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                           ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------+
; |qiangdaqi                                ; 178 (0)     ; 53           ; 0           ; 47   ; 125 (0)      ; 9 (0)             ; 44 (0)           ; 8 (0)           ; 0 (0)      ; |qiangdaqi                                                                    ;
;    |qiangda:inst2|                        ; 46 (38)     ; 20           ; 0           ; 0    ; 26 (26)      ; 1 (1)             ; 19 (11)          ; 8 (0)           ; 0 (0)      ; |qiangdaqi|qiangda:inst2                                                      ;
;       |lpm_counter:cnt_rtl_0|             ; 8 (0)       ; 8            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 8 (0)            ; 8 (0)           ; 0 (0)      ; |qiangdaqi|qiangda:inst2|lpm_counter:cnt_rtl_0                                ;
;          |alt_counter_f10ke:wysi_counter| ; 8 (8)       ; 8            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 8 (8)            ; 8 (8)           ; 0 (0)      ; |qiangdaqi|qiangda:inst2|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter ;
;    |score:inst|                           ; 132 (132)   ; 33           ; 0           ; 0    ; 99 (99)      ; 8 (8)             ; 25 (25)          ; 0 (0)           ; 0 (0)      ; |qiangdaqi|score:inst                                                         ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 53    ;
; Number of registers using Synchronous Clear  ; 8     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 52    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 47    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; score:inst|score1[4]                   ; 7       ;
; score:inst|score2[4]                   ; 7       ;
; score:inst|score3[4]                   ; 7       ;
; score:inst|score4[4]                   ; 7       ;
; qiangda:inst2|delay                    ; 4       ;
; score:inst|flag                        ; 10      ;
; Total number of inverted registers = 6 ;         ;
+----------------------------------------+---------+


+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: qiangda:inst2|lpm_counter:cnt_rtl_0 ;
+------------------------+-------------------+-----------------------------------------+
; Parameter Name         ; Value             ; Type                                    ;
+------------------------+-------------------+-----------------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                              ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                            ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                            ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                          ;
; LPM_WIDTH              ; 8                 ; Untyped                                 ;
; LPM_DIRECTION          ; UP                ; Untyped                                 ;
; LPM_MODULUS            ; 0                 ; Untyped                                 ;
; LPM_AVALUE             ; UNUSED            ; Untyped                                 ;
; LPM_SVALUE             ; UNUSED            ; Untyped                                 ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                                 ;
; DEVICE_FAMILY          ; FLEX10K           ; Untyped                                 ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                                 ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH                      ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK                      ;
; CARRY_CNT_EN           ; SMART             ; Untyped                                 ;
; LABWIDE_SCLR           ; ON                ; Untyped                                 ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                                 ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                                 ;
+------------------------+-------------------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Jun 28 00:09:07 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off qiangdaqi -c qiangdaqi
Info: Found 1 design units, including 1 entities, in source file qiangda.v
    Info: Found entity 1: qiangda
Info: Found 1 design units, including 1 entities, in source file score.v
    Info: Found entity 1: score
Info: Found 1 design units, including 1 entities, in source file qiangdaqi.bdf
    Info: Found entity 1: qiangdaqi
Info: Elaborating entity "qiangdaqi" for the top level hierarchy
Info: Elaborating entity "qiangda" for hierarchy "qiangda:inst2"
Info: Elaborating entity "score" for hierarchy "score:inst"
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: "qiangda:inst2|cnt[0]~8"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus 6.0/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "qiangda:inst2|lpm_counter:cnt_rtl_0"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus 6.0/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "qiangda:inst2|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "qiangda:inst2|lpm_counter:cnt_rtl_0"
Info: Instantiated megafunction "qiangda:inst2|lpm_counter:cnt_rtl_0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Registers with preset signals will power-up high
Info: Implemented 225 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 37 output pins
    Info: Implemented 178 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Jun 28 00:09:10 2007
    Info: Elapsed time: 00:00:04