qiangdaqi.tan.rpt

用verilog hdl硬件描述语言实现多人抢答器功能

; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPF10K10LC84-4     ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk1            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; clk2            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk1'                                                                                                                                                                                                                                                                        ;
+-------+------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                      ; To                                                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 41.84 MHz ( period = 23.900 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; alarm_ahead                                               ; clk1       ; clk1     ; None                        ; None                      ; 20.200 ns               ;
; N/A   ; 41.84 MHz ( period = 23.900 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; alarm_ahead                                               ; clk1       ; clk1     ; None                        ; None                      ; 20.200 ns               ;
; N/A   ; 41.84 MHz ( period = 23.900 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; alarm_ahead                                               ; clk1       ; clk1     ; None                        ; None                      ; 20.200 ns               ;
; N/A   ; 42.19 MHz ( period = 23.700 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; result4~reg0                                              ; clk1       ; clk1     ; None                        ; None                      ; 20.200 ns               ;
; N/A   ; 42.19 MHz ( period = 23.700 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; result4~reg0                                              ; clk1       ; clk1     ; None                        ; None                      ; 20.200 ns               ;
; N/A   ; 42.19 MHz ( period = 23.700 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; result4~reg0                                              ; clk1       ; clk1     ; None                        ; None                      ; 20.200 ns               ;
; N/A   ; 42.74 MHz ( period = 23.400 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; alarm_ahead                                               ; clk1       ; clk1     ; None                        ; None                      ; 19.700 ns               ;
; N/A   ; 42.74 MHz ( period = 23.400 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; alarm_ahead                                               ; clk1       ; clk1     ; None                        ; None                      ; 19.700 ns               ;
; N/A   ; 42.74 MHz ( period = 23.400 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; alarm_ahead                                               ; clk1       ; clk1     ; None                        ; None                      ; 19.700 ns               ;
; N/A   ; 42.74 MHz ( period = 23.400 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; alarm_ahead                                               ; clk1       ; clk1     ; None                        ; None                      ; 19.700 ns               ;
; N/A   ; 43.10 MHz ( period = 23.200 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; result4~reg0                                              ; clk1       ; clk1     ; None                        ; None                      ; 19.700 ns               ;
; N/A   ; 43.10 MHz ( period = 23.200 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; result4~reg0                                              ; clk1       ; clk1     ; None                        ; None                      ; 19.700 ns               ;
; N/A   ; 43.10 MHz ( period = 23.200 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; result4~reg0                                              ; clk1       ; clk1     ; None                        ; None                      ; 19.700 ns               ;
; N/A   ; 43.10 MHz ( period = 23.200 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; result4~reg0                                              ; clk1       ; clk1     ; None                        ; None                      ; 19.700 ns               ;
; N/A   ; 43.48 MHz ( period = 23.000 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; result2~reg0                                              ; clk1       ; clk1     ; None                        ; None                      ; 19.500 ns               ;
; N/A   ; 43.48 MHz ( period = 23.000 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; result2~reg0                                              ; clk1       ; clk1     ; None                        ; None                      ; 19.500 ns               ;
; N/A   ; 43.48 MHz ( period = 23.000 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; result2~reg0                                              ; clk1       ; clk1     ; None                        ; None                      ; 19.500 ns               ;
; N/A   ; 43.67 MHz ( period = 22.900 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; alarm_ahead                                               ; clk1       ; clk1     ; None                        ; None                      ; 19.200 ns               ;
; N/A   ; 44.05 MHz ( period = 22.700 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; result4~reg0                                              ; clk1       ; clk1     ; None                        ; None                      ; 19.200 ns               ;
; N/A   ; 44.44 MHz ( period = 22.500 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; result2~reg0                                              ; clk1       ; clk1     ; None                        ; None                      ; 19.000 ns               ;
; N/A   ; 44.44 MHz ( period = 22.500 ns )               ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; result2~reg0                                              ; clk1       ; clk1     ; None                        ; None                      ; 19.000 ns               ;