qiangdaqi.tan.summary

用verilog hdl硬件描述语言实现多人抢答器功能

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 14.400 ns
From           : k1
To             : result4~reg0
From Clock     : --
To Clock       : clk1
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 17.900 ns
From           : alarm_ahead
To             : alarm
From Clock     : clk1
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 15.300 ns
From           : clk2
To             : alarm
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.700 ns
From           : k1
To             : result1~reg0
From Clock     : --
To Clock       : clk1
Failed Paths   : 0

Type           : Clock Setup: 'clk1'
Slack          : N/A
Required Time  : None
Actual Time    : 41.84 MHz ( period = 23.900 ns )
From           : lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[4]
To             : alarm_ahead
From Clock     : clk1
To Clock       : clk1
Failed Paths   : 0

Type           : Clock Setup: 'clk2'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 125.00 MHz ( period = 8.000 ns )
From           : clk3
To             : clk3
From Clock     : clk2
To Clock       : clk2
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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