readme.txt

ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）

The sim folder has sample test_bench files to simulate the designs in Modelsim environment. 
This folder has the memory model, test bench file and required parameter file/files. 
Read the steps in this file before simulations are done.

To run simulations for this sample configuration, user has to generate the RTL from the tool for the following GUI 
options.

Data_width                : 16
HDL                       : Verilog 
Memory configuration      : x16
DIMM/Component            : Component 
Memory Part No            : MT46V32M16P-5B
Add test bench            : Yes
Use DCM                   : Yes
Number of controllers     : 1

-----------------------------------------------For Verilog----------------------------------------------------------

1. After the design is generated change the name of the top level module name 'board_file' in the 'ddr1_test_tb' module 
   with the module name the user generated from the MIG tool.
  
2. After the rtl is generated, create the Model sim project file. Add all the rtl files from the rtl folder 
   to the project Also add the memory model, test bench and glbl files from the sim folder. 

3. Compile the design.

4. After successful compilation of design, load the design using the following comamnd. 

   vsim -t ps +notimingchecks -L ../Modeltech_6.1a/unisims_ver work.ddr1_test_tb glbl
   Note : User should set proper path for unisim verilog libraries

5. After the design is successfully loaded, run the simulations and view the waveforms. 


Notes : To run simulations for different data widths and configurations, users should modify the test bench files
with right memory models and design files. User should modify the sys_clk_in and sys_clk_in_L frequency in test bench according to the frequency selected for the design.