adr_cntrl_timingsheet_0.xls

ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）

Uncertainity parameter                       	Value                                  	Uncertainity before DQS             	Uncertainity after DQS              	Meaning
Tclock                                       	10000.00                               	                                        	                                        	clock period
Memory address and control input setup time  	600                                  	600                               	0                               	
Memory address and control input hold time   	600                                  	0                               	600                               	
Tpackage_skew                                	20                               	10                        	10                        	Package skew
Clock jitter                                 	0                                  	0                               	0                               	Same DCM is used to generate DQ and DQS
Clock_tree_skew                              	100                                	100                         	100                         	Small value considered for skew on global clock line since detection of DQS and associated DQ are placed close to each other
Tclock_out_phase                             	140                                	140                         	140                         	Phase offset error between different clock outputs of the same DCM
Pcb_layout_skew                              	400                               	400                        	400                        	Skew between data lines and asociated strobe on the board
Data valid window - min/max                  	8140.00                    	1250.00             	1250.00             	Valid data window
Margin                                       	7500.00