log.txt

ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）

                                                          Log file                                                       

Generated by mig version 1.6 at 星期四 七月 5 14:43:22 2007


Reading design libraries of xc4vsx35-ff668... successful !
Clearing output directory E:/ddr/ddr successful! 
Removing E:/ddr/ddr/mem_interface_top_withouttb/rtl successful! 
Removing E:/ddr/ddr/mem_interface_top_withouttb/par successful! 
Removing E:/ddr/ddr/mem_interface_top_withouttb/synth successful! 
Removing E:/ddr/ddr/mem_interface_top_withouttb/sim successful! 
Removing E:/ddr/ddr/mem_interface_top_withouttb/docs successful! 
Removing E:/ddr/ddr/mem_interface_top_withouttb successful! 
Creating the directory E:/ddr/ddr/mem_interface_top_withouttb...successful!
Creating the directory E:/ddr/ddr/mem_interface_top_withouttb/par...successful!
Creating the directory E:/ddr/ddr/mem_interface_top_withouttb/docs ...successful! 
Creating the directory E:/ddr/ddr/mem_interface_top_withouttb/synth ...successful! 
Creating the directory E:/ddr/ddr/mem_interface_top_withouttb/sim ...successful! 
Creating the directory E:/ddr/ddr/mem_interface_top_withouttb/rtl ...successful! 
Creating the file E:/ddr/ddr/mem_interface_top_withouttb/par/mem_interface_top.ucf  ...successful!
Writing the headers to E:/ddr/ddr/mem_interface_top_withouttb/par/mem_interface_top.ucf  ...successful!
Writing the dcm constraints to E:/ddr/ddr/mem_interface_top_withouttb/par/mem_interface_top.ucf  ...successful!

/*******************************************************/
/*                 Controller  0                       */
/*******************************************************/
Cloning Data bits  ...successful!
Cloning Strobe bits  ...successful!
Cloning Mask bits  ...successful!
Cloning Clock bits  ...successful!
Cloning user_interface bits  ...successful!
Cloning user_interface bits  ...successful!
Cloning user_interface bits  ...successful!
Removing unwanted signal names from MT46V16M16P-5B...successful!
Assigning pins for data signals,strobes, Read enables, clocks and data masks ...successful!
Assigning pins for memory clock signals ...successful!
Assigning pins for address signals ...successful!
Assigning pins for bank address signals ...successful!
Assigning pins for memory control signals ...successful!
Assigning pins to system control signals  ...successful!
Assigning pins to system clock signals  ...successful!
Copying all the files from docs ...
copying d:/Xilinx/coregen/ip/xilinx/other/com/xilinx/ip/mig_v1_6/bin/nt/../../data/docs/virtex4/DDR SDRAM/xapp701.pdf to E:/ddr/ddr/mem_interface_top_withouttb/docs ...successful!
copying d:/Xilinx/coregen/ip/xilinx/other/com/xilinx/ip/mig_v1_6/bin/nt/../../data/docs/virtex4/DDR SDRAM/xapp709.pdf to E:/ddr/ddr/mem_interface_top_withouttb/docs ...successful!
 ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_data_tap_inc.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_idelay_ctrl.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_data_write_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_rd_wr_addr_fifo_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_ddr_controller_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_data_path_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_iobs_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_rd_data_fifo_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_user_interface_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_parameters_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_top_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_backend_fifos_0.vhd and 
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_wr_data_fifo_16.vhd ...successful!
 ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_ddr_controller_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_controller_iobs_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_data_path_iobs_0.vhd and 
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_v4_dm_iob.vhd ...successful!
 ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_infrastructure_iobs_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_RAM_D_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_rd_data_0.vhd and 
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_pattern_compare8.vhd ...successful!
 ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_tap_logic_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_ucf_constraints_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_v4_dq_iob.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_v4_dqs_iob.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_infrastructure.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_rd_wr_addr_fifo_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_tap_ctrl_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/synth/mem_interface_top_dcm_constraints.sdc ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top_sdc_constraints_0.vhd ...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/par/mem_interface_top.ucf
...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/par/mem_interface_top.ucf...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/synth/mem_interface_top.sdc...successful!
Generating the file E:/ddr/ddr/mem_interface_top_withouttb/rtl/mem_interface_top.vhd......successful! 


Result:
		Successful!
The design output files are located in E:/ddr/ddr/mem_interface_top_withouttb/rtl and ..mem_interface_top_withouttb/par for rtl & ucf files.