read_timingsheet_0.xls

ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）

Uncertainity parameter                     	V4-10                               	V4-11                            	V4-12                         	Meaning
Tclock                                     	10000.00                           	10000.00                        	10000.00                        	Clock period
Tphase                                     	5000.00                    	5000.00                 	5000.00                 	Data period, half of the clock period
Tmemory_dll_duty_cycle_dist                	150      	150   	150   	Clock jitter from memory datasheets
Memory uncertainities                      	1400.00                           	1400.00                        	1400.00                        	This parameter considers the worst of all the memory parameters since there is overlap between these parameters(Tdsq,Tqhs,Tdqsk,Tac)
Tsamp                                      	550                              	500                           	450                           	
Tpcb_layout_skew                           	50                  	50               	50               	
Tpackage_skew                              	20                    	20                 	20                 	Package skew
Clock_tree_skew                            	100                  	100               	100               	
Number of taps in data valid window        	100.00                 	100.00              	100.00              	
Idelay_jitter                              	1200.00                    	1200.00                 	1200.00                 	
Data valid window value in ps.             	1530.00                 	1580.00              	1630.00