write_timingsheet_0.xls

ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）

Uncertainity parameter                       	Value                                  	Uncertainity before DQS             	Uncertainity after DQS              	Meaning
Tclock                                       	10000.00                               	                                        	                                        	clock period
Tmemory_dll_duty_cycle_dist                  	500.00          	500.00                          	500.00                          	Duty cycle distortion from memory DLL is subtracted from clock phase(equal to halfclock period) to determine Tdata_period
Tdata_period                                 	4500.00                         	                                        	                                        	Data period is half the clock period with 10% duty cycle duty distortion subtracted from it
Data setup time relative to strobe or clock  	400                                  	400                           	0                           	Due to overlap with other parameters only the worstcase value is considered
Data hold time relative to strobe or clock   	400                                  	0                           	400                           	Due to overlap with other parameters only the worstcase value is considered
Tpackage_skew                                	20                               	10                        	10                        	Package skew
Clock jitter                                 	0                                  	0                               	0                               	Same DCM is used to generate DQ and DQS
Clock_tree_skew                              	100                                	100                         	100                         	Small value considered for skew on global clock line since detection of DQS and associated DQ are placed close to each other
Tclock_out_phase                             	140                                	140                         	140                         	Phase offset error between different clock outputs of the same DCM
Pcb_layout_skew                              	20                               	20                        	20                        	Skew between data lines and asociated strobe on the board
Uncertainities                               	1080.00                       	670.00                	670.00                	
Window                                       	3160.00                               	670.00                        	3830.00                        	Valid data window