ddr.cgp

ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）

# Date: Thu Jul 05 03:23:36 2007
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = False
SET workingdirectory = E:\ddr\ddr\tmp
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
SET device = xc4vsx35
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = ff668
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex4
SET formalverification = False
SET removerpms = False