pointer_tb.vhd

来自「FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进」· VHDL 代码 · 共 54 行

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;
--use work.all;

ENTITY pointer_tb IS
END pointer_tb;

ARCHITECTURE behavial of pointer_tb IS
COMPONENT writer_pointer 
port(		
        wclk   :   IN   std_logic;
        rstb   :   IN   std_logic;
        wload  :   IN   std_logic;
        wenb   :   IN   std_logic;
        wldata :   IN   std_logic_vector(4 DOWNTO 0);
        
        waddr  :   OUT  std_logic_vector(4 DOWNTO 0)
);
END COMPONENT;

COMPONENT reader_pointer 
port(		
        rclk   :   IN   std_logic;
        rstb   :   IN   std_logic;
        rload  :   IN   std_logic;
        renb   :   IN   std_logic;
        rldata :   IN   std_logic_vector(4 DOWNTO 0);
        
        raddr  :   OUT  std_logic_vector(4 DOWNTO 0)
);
END COMPONENT;

signal s1,s2,s3, sclk : std_logic := '0';
signal sdin, sdout, sinit: std_logic_vector(4 downto 0) := "00000";
BEGIN

WCOUNTER: writer_pointer port map(
   wclk =>sclk, rstb=>s3, wload =>s1, wenb => s2, wldata => sinit, waddr=>sdout
);

--RCOUNTER: reader_pointer port map(
--  rclk =>sclk, rstb=>s3, rload =>s1, renb => s2, rldata => sinit, raddr=>sdout
--);

sclk <= not sclk after 50 ns;
s1 <= '1' after 3200 ns;
sinit <= "00101" after 3200 ns;
s2 <= '1' after 60 ns;
s3 <= '1' after 60 ns, '0' after 5000 ns;

END behavial;