syn_tb.vhd.bak

来自「FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进」· BAK 代码 · 共 46 行

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;
--use work.all;

ENTITY syn_tb IS
END syn_tb;

ARCHITECTURE behavial of syn_tb IS
COMPONENT synchronizer
port(	
	wclk: IN std_logic;
	rclk: IN std_logic;
	rstb: IN std_logic;

	wr_done: IN std_logic;
	rd_done: IN std_logic;

	fullemptyb: OUT std_logic;
	fullemptyb_sync_pulse: OUT std_logic    
);
END COMPONENT; 

signal sclk1, sclk2 : std_logic := '0';
signal s0 : std_logic := '0';
signal feb, febpulse : std_logic := '0';
signal writerdone, readerdone: std_logic := '0';

BEGIN

--Test Synchronizer
Sync01: synchronizer port map(
   wclk => sclk1, rclk => sclk2, rstb => s0, 
   wr_done => writerdone, rd_done => readerdone,
   fullemptyb => feb, fullemptyb_sync_pulse => febpulse
);

sclk1 <= not sclk1 after 50 ns; -- writer clock
sclk2 <= not sclk2 after 100 ns; -- reader clock

s0 <= '1' after 60 ns, '0' after 5000 ns; -- rstb

wr_done <= '1' after 150 ns, '0' after 250 ns;
rd_done <= '1' after 400 ns, '0' after 600 ns;

END behavial;