reader_pointer.vhd

来自「FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进」· VHDL 代码 · 共 64 行

-- The Reader Pointer will control the Reader operation

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--use IEEE.std_logic_arith.all;

ENTITY reader_pointer IS
    PORT(
        rclk   :   IN   std_logic;
        rstb   :   IN   std_logic;
        rload  :   IN   std_logic;
        renb   :   IN   std_logic;
        rldata :   IN   std_logic_vector(4 DOWNTO 0);
        
        raddr  :   OUT  std_logic_vector(4 DOWNTO 0)
        );
END reader_pointer;

ARCHITECTURE behav OF reader_pointer IS
SIGNAL loadflag   :   std_logic;
SIGNAL enbflag   :   std_logic;
SIGNAL counter   :   unsigned(4 DOWNTO 0);
BEGIN
    rcounter: PROCESS (rstb, rclk)
    BEGIN
        IF (rstb /= '1') THEN
            counter <= (OTHERS => '0');
        ELSIF (rclk'EVENT AND rclk = '1') THEN
            IF (loadflag = '1') THEN
                --counter <= (OTHERS => '0');
                counter <= UNSIGNED(rldata);
            ELSIF (enbflag = '1') THEN
                counter <= counter + 1;
            ELSE
                counter <= counter;
            END IF;
            
            raddr <= std_logic_vector(counter);
        END IF;
    END PROCESS;
    
    rcomb: PROCESS (counter,rload, renb)
    BEGIN
         --ALL_ONES(counter'LENGTH - 1 DOWNTO 0)
        IF (counter > "11111" OR rload = '1') THEN
            loadflag <= '1';
        ELSE
            loadflag <= '0';
        END IF;
        
        IF (renb = '1') THEN
            enbflag <= '1';
        ELSE
            enbflag <= '0';
        END IF;
    
    END PROCESS;
    
    --raddr <= std_logic_vector(counter);
    
END behav;