taix_fee.tan.qmsg

verilog HDL编写的出租车计费系统

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "a 3 " "Warning: Circuit may not operate. Detected 3 non-operational path(s) clocked by clock \"a\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "qdd:qdd1\|b qdd:qdd1\|k2o a 500 ps " "Info: Found hold time violation between source  pin or register \"qdd:qdd1\|b\" and destination pin or register \"qdd:qdd1\|k2o\" for clock \"a\" (Hold time is 500 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.800 ns + Largest " "Info: + Largest clock skew is 0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "a destination 3.200 ns + Longest register " "Info: + Longest clock path from clock \"a\" to destination register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns a 1 CLK PIN_79 133 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_79; Fanout = 133; CLK Node = 'a'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "taix_fee" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/taix_fee/db/taix_fee.quartus_db" { Floorplan "C:/Documents and Settings/user/桌面/taix_fee/" "" "" { a } "NODE_NAME" } "" } } { "taix_fee.v" "" { Text "C:/Documents and Settings/user/桌面/taix_fee/taix_fee.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns qdd:qdd1\|f1 2 REG LC6_B1 4 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC6_B1; Fanout = 4; REG Node = 'qdd:qdd1\|f1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "taix_fee" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/taix_fee/db/taix_fee.quartus_db" { Floorplan "C:/Documents and Settings/user/桌面/taix_fee/" "" "0.900 ns" { a qdd:qdd1|f1 } "NODE_NAME" } "" } } { "qdd.v" "" { Text "C:/Documents and Settings/user/桌面/taix_fee/qdd.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 3.200 ns qdd:qdd1\|k2o 3 REG LC4_B1 1 " "Info: 3: + IC(0.300 ns) + CELL(0.000 ns) = 3.200 ns; Loc. = LC4_B1; Fanout = 1; REG Node = 'qdd:qdd1\|k2o'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "taix_fee" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/taix_fee/db/taix_fee.quartus_db" { Floorplan "C:/Documents and Settings/user/桌面/taix_fee/" "" "0.300 ns" { qdd:qdd1|f1 qdd:qdd1|k2o } "NODE_NAME" } "" } } { "qdd.v" "" { Text "C:/Documents and Settings/user/桌面/taix_fee/qdd.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns ( 78.13 % ) " "Info: Total cell delay = 2.500 ns ( 78.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.700 ns ( 21.88 % ) " "Info: Total interconnect delay = 0.700 ns ( 21.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "taix_fee" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/taix_fee/db/taix_fee.quartus_db" { Floorplan "C:/Documents and Settings/user/桌面/taix_fee/" "" "3.200 ns" { a qdd:qdd1|f1 qdd:qdd1|k2o } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.200 ns" { a a~out qdd:qdd1|f1 qdd:qdd1|k2o } { 0.000ns 0.000ns 0.400ns 0.300ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "a source 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"a\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns a 1 CLK PIN_79 133 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_79; Fanout = 133; CLK Node = 'a'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "taix_fee" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/taix_fee/db/taix_fee.quartus_db" { Floorplan "C:/Documents and Settings/user/桌面/taix_fee/" "" "" { a } "NODE_NAME" } "" } } { "taix_fee.v" "" { Text "C:/Documents and Settings/user/桌面/taix_fee/taix_fee.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns qdd:qdd1\|b 2 REG LC8_B1 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC8_B1; Fanout = 1; REG Node = 'qdd:qdd1\|b'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "taix_fee" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/taix_fee/db/taix_fee.quartus_db" { Floorplan "C:/Documents and Settings/user/桌面/taix_fee/" "" "0.400 ns" { a qdd:qdd1|b } "NODE_NAME" } "" } } { "qdd.v" "" { Text "C:/Documents and Settings/user/桌面/taix_fee/qdd.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "taix_fee" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/taix_fee/db/taix_fee.quartus_db" { Floorplan "C:/Documents and Settings/user/桌面/taix_fee/" "" "2.400 ns" { a qdd:qdd1|b } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { a a~out qdd:qdd1|b } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "taix_fee" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/taix_fee/db/taix_fee.quartus_db" { Floorplan "C:/Documents and Settings/user/桌面/taix_fee/" "" "3.200 ns" { a qdd:qdd1|f1 qdd:qdd1|k2o } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.200 ns" { a a~out qdd:qdd1|f1 qdd:qdd1|k2o } { 0.000ns 0.000ns 0.400ns 0.300ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "taix_fee" "UNKNOWN" "V1" "C:/Documents and Settings/user/桌面/taix_fee/db/taix_fee.quartus_db" { Floorplan "C:/Documents and Settings/user/桌面/taix_fee/" "" "2.400 ns" { a qdd:qdd1|b } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { a a~out qdd:qdd1|b } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns - " "Info: - Micro clock to output delay of source is 0.500 ns" {  } { { "qdd.v" "" { Text "C:/Documents and Settings/user/桌面/taix_fee/qdd.v" 4 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.100 ns - Shortest register register " "Info: - Shortest register to register delay is 1.100 ns