taix_fee.fit.summary

来自「verilog HDL编写的出租车计费系统」· SUMMARY 代码 · 共 12 行

Fitter Status : Successful - Fri Jul 13 15:12:10 2007
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : taix_fee
Top-level Entity Name : taix_fee
Family : ACEX1K
Device : EP1K30QC208-3
Timing Models : Final
Total logic elements : 454 / 1,728 ( 26 % )
Total pins : 20 / 147 ( 14 % )
Total memory bits : 0 / 24,576 ( 0 % )
Total PLLs : 0