reg4.tan.summary

用VHDL 语言描述频率计的设计

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.043 ns
From           : DIN[2]
To             : DOUT[2]~reg0
From Clock     : --
To Clock       : LOAD
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.775 ns
From           : DOUT[1]~reg0
To             : DOUT[1]
From Clock     : LOAD
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.359 ns
From           : DIN[1]
To             : DOUT[1]~reg0
From Clock     : --
To Clock       : LOAD
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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