reg4.fit.eqn

用VHDL 语言描述频率计的设计

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--A1L8Q is DOUT[0]~reg0 at LC_X2_Y13_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L8Q_lut_out = GND;
A1L8Q = DFFEAS(A1L8Q_lut_out, GLOBAL(LOAD), VCC, , , DIN[0], , , VCC);


--A1L10Q is DOUT[1]~reg0 at LC_X26_Y12_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L10Q_lut_out = GND;
A1L10Q = DFFEAS(A1L10Q_lut_out, GLOBAL(LOAD), VCC, , , DIN[1], , , VCC);


--A1L12Q is DOUT[2]~reg0 at LC_X20_Y13_N2
--operation mode is normal

A1L12Q_lut_out = DIN[2];
A1L12Q = DFFEAS(A1L12Q_lut_out, GLOBAL(LOAD), VCC, , , , , , );


--A1L14Q is DOUT[3]~reg0 at LC_X1_Y12_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L14Q_lut_out = GND;
A1L14Q = DFFEAS(A1L14Q_lut_out, GLOBAL(LOAD), VCC, , , DIN[3], , , VCC);


--DIN[0] is DIN[0] at PIN_2
--operation mode is input

DIN[0] = INPUT();


--LOAD is LOAD at PIN_17
--operation mode is input

LOAD = INPUT();


--DIN[1] is DIN[1] at PIN_106
--operation mode is input

DIN[1] = INPUT();


--DIN[2] is DIN[2] at PIN_121
--operation mode is input

DIN[2] = INPUT();


--DIN[3] is DIN[3] at PIN_3
--operation mode is input

DIN[3] = INPUT();


--DOUT[0] is DOUT[0] at PIN_143
--operation mode is output

DOUT[0] = OUTPUT(A1L8Q);


--DOUT[1] is DOUT[1] at PIN_112
--operation mode is output

DOUT[1] = OUTPUT(A1L10Q);


--DOUT[2] is DOUT[2] at PIN_119
--operation mode is output

DOUT[2] = OUTPUT(A1L12Q);


--DOUT[3] is DOUT[3] at PIN_4
--operation mode is output

DOUT[3] = OUTPUT(A1L14Q);