reg4.tan.qmsg

用VHDL 语言描述频率计的设计

{ "Info" "ITDB_TSU_RESULT" "DOUT\[2\]~reg0 DIN\[2\] LOAD 4.043 ns register " "Info: tsu for register \"DOUT\[2\]~reg0\" (data pin = \"DIN\[2\]\", clock pin = \"LOAD\") is 4.043 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.787 ns + Longest pin register " "Info: + Longest pin to register delay is 6.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns DIN\[2\] 1 PIN PIN_121 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_121; Fanout = 1; PIN Node = 'DIN\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "" { DIN[2] } "NODE_NAME" } "" } } { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/寄存器/REG4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.003 ns) + CELL(0.309 ns) 6.787 ns DOUT\[2\]~reg0 2 REG LC_X20_Y13_N2 1 " "Info: 2: + IC(5.003 ns) + CELL(0.309 ns) = 6.787 ns; Loc. = LC_X20_Y13_N2; Fanout = 1; REG Node = 'DOUT\[2\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "5.312 ns" { DIN[2] DOUT[2]~reg0 } "NODE_NAME" } "" } } { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/寄存器/REG4.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.784 ns ( 26.29 % ) " "Info: Total cell delay = 1.784 ns ( 26.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.003 ns ( 73.71 % ) " "Info: Total interconnect delay = 5.003 ns ( 73.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "6.787 ns" { DIN[2] DOUT[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.787 ns" { DIN[2] DIN[2]~out0 DOUT[2]~reg0 } { 0.000ns 0.000ns 5.003ns } { 0.000ns 1.475ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/寄存器/REG4.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LOAD destination 2.781 ns - Shortest register " "Info: - Shortest clock path from clock \"LOAD\" to destination register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns LOAD 1 CLK PIN_17 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'LOAD'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "" { LOAD } "NODE_NAME" } "" } } { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/寄存器/REG4.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns DOUT\[2\]~reg0 2 REG LC_X20_Y13_N2 1 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X20_Y13_N2; Fanout = 1; REG Node = 'DOUT\[2\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "1.312 ns" { LOAD DOUT[2]~reg0 } "NODE_NAME" } "" } } { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/寄存器/REG4.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "2.781 ns" { LOAD DOUT[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { LOAD LOAD~out0 DOUT[2]~reg0 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "6.787 ns" { DIN[2] DOUT[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.787 ns" { DIN[2] DIN[2]~out0 DOUT[2]~reg0 } { 0.000ns 0.000ns 5.003ns } { 0.000ns 1.475ns 0.309ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "2.781 ns" { LOAD DOUT[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { LOAD LOAD~out0 DOUT[2]~reg0 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "LOAD DOUT\[1\] DOUT\[1\]~reg0 6.775 ns register " "Info: tco from clock \"LOAD\" to destination pin \"DOUT\[1\]\" through register \"DOUT\[1\]~reg0\" is 6.775 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LOAD source 2.781 ns + Longest register " "Info: + Longest clock path from clock \"LOAD\" to source register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns LOAD 1 CLK PIN_17 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'LOAD'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "" { LOAD } "NODE_NAME" } "" } } { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/寄存器/REG4.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns DOUT\[1\]~reg0 2 REG LC_X26_Y12_N2 1 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y12_N2; Fanout = 1; REG Node = 'DOUT\[1\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "1.312 ns" { LOAD DOUT[1]~reg0 } "NODE_NAME" } "" } } { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/寄存器/REG4.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "2.781 ns" { LOAD DOUT[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { LOAD LOAD~out0 DOUT[1]~reg0 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/寄存器/REG4.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.770 ns + Longest register pin " "Info: + Longest register to pin delay is 3.770 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DOUT\[1\]~reg0 1 REG LC_X26_Y12_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y12_N2; Fanout = 1; REG Node = 'DOUT\[1\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "" { DOUT[1]~reg0 } "NODE_NAME" } "" } } { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/寄存器/REG4.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.662 ns) + CELL(2.108 ns) 3.770 ns DOUT\[1\] 2 PIN PIN_112 0 " "Info: 2: + IC(1.662 ns) + CELL(2.108 ns) = 3.770 ns; Loc. = PIN_112; Fanout = 0; PIN Node = 'DOUT\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "3.770 ns" { DOUT[1]~reg0 DOUT[1] } "NODE_NAME" } "" } } { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/寄存器/REG4.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 55.92 % ) " "Info: Total cell delay = 2.108 ns ( 55.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.662 ns ( 44.08 % ) " "Info: Total interconnect delay = 1.662 ns ( 44.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "3.770 ns" { DOUT[1]~reg0 DOUT[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.770 ns" { DOUT[1]~reg0 DOUT[1] } { 0.000ns 1.662ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "2.781 ns" { LOAD DOUT[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { LOAD LOAD~out0 DOUT[1]~reg0 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "3.770 ns" { DOUT[1]~reg0 DOUT[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.770 ns" { DOUT[1]~reg0 DOUT[1] } { 0.000ns 1.662ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "DOUT\[1\]~reg0 DIN\[1\] LOAD -3.359 ns register " "Info: th for register \"DOUT\[1\]~reg0\" (data pin = \"DIN\[1\]\", clock pin = \"LOAD\") is -3.359 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LOAD destination 2.781 ns + Longest register " "Info: + Longest clock path from clock \"LOAD\" to destination register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns LOAD 1 CLK PIN_17 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'LOAD'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "" { LOAD } "NODE_NAME" } "" } } { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/寄存器/REG4.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns DOUT\[1\]~reg0 2 REG LC_X26_Y12_N2 1 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y12_N2; Fanout = 1; REG Node = 'DOUT\[1\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "1.312 ns" { LOAD DOUT[1]~reg0 } "NODE_NAME" } "" } } { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/寄存器/REG4.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "2.781 ns" { LOAD DOUT[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { LOAD LOAD~out0 DOUT[1]~reg0 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/寄存器/REG4.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.155 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.155 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DIN\[1\] 1 PIN PIN_106 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_106; Fanout = 1; PIN Node = 'DIN\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "" { DIN[1] } "NODE_NAME" } "" } } { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/寄存器/REG4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.571 ns) + CELL(0.115 ns) 6.155 ns DOUT\[1\]~reg0 2 REG LC_X26_Y12_N2 1 " "Info: 2: + IC(4.571 ns) + CELL(0.115 ns) = 6.155 ns; Loc. = LC_X26_Y12_N2; Fanout = 1; REG Node = 'DOUT\[1\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "4.686 ns" { DIN[1] DOUT[1]~reg0 } "NODE_NAME" } "" } } { "REG4.vhd" "" { Text "F:/临时/EDA/课程设计/寄存器/REG4.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 25.74 % ) " "Info: Total cell delay = 1.584 ns ( 25.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.571 ns ( 74.26 % ) " "Info: Total interconnect delay = 4.571 ns ( 74.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "6.155 ns" { DIN[1] DOUT[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.155 ns" { DIN[1] DIN[1]~out0 DOUT[1]~reg0 } { 0.000ns 0.000ns 4.571ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "2.781 ns" { LOAD DOUT[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { LOAD LOAD~out0 DOUT[1]~reg0 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "REG4" "UNKNOWN" "V1" "F:/临时/EDA/课程设计/寄存器/db/REG4.quartus_db" { Floorplan "F:/临时/EDA/课程设计/寄存器/" "" "6.155 ns" { DIN[1] DOUT[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.155 ns" { DIN[1] DIN[1]~out0 DOUT[1]~reg0 } { 0.000ns 0.000ns 4.571ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 12 15:34:44 2007 " "Info: Processing ended: Tue Jun 12 15:34:44 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}